Freescale-semiconductor MCF5480 Manuale Utente

MCF548x Reference ManualDevices Supported:MCF5485 MCF5482MCF5484 MCF5481MCF5483 MCF5480Document Number: MCF5485RMRev. 301/2006

MCF548x Reference Manual, Rev. 3x Freescale SemiconductorContentsParagraphNumberTitlePageNumber3.7.4 Miscellaneous Instruction Execution Timing ...

MCF548x Reference Manual, Rev. 32-30 Freescale Semiconductor2.2.15.4 Breakpoint/Test Mode Select (BKPT/TMS)If MTMOD0 is low, BKPT is selected. BKPT si

MCF548x Reference Manual, Rev. 331-10 Freescale SemiconductorFigure 31-3 shows the pinout for the lower left quadrant of the MCF5485/MCF5484 pinout fo

Mechanical Diagrams MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-11Figure 31-4 shows the pinout for the lower left quadrant of the MCF5

MCF548x Reference Manual, Rev. 331-12 Freescale Semiconductor31.3.2 MCF5483/5482 Mechanical DiagramFigure 31-5–Figure 31-8 show the pinout for the eac

Mechanical Diagrams MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-13Figure 31-6 shows the pinout for the upper right quadrant of the MCF

MCF548x Reference Manual, Rev. 331-14 Freescale SemiconductorFigure 31-7 shows the pinout for the lower left quadrant of the MCF5483/MCF5482 pinout fo

Mechanical Diagrams MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-15Figure 31-8 shows the pinout for the lower left quadrant of the MCF5

MCF548x Reference Manual, Rev. 331-16 Freescale Semiconductor31.4 MCF5481/5480 Mechanical DiagramFigure 31-9–Figure 31-12 show the pinout for the each

MCF5481/5480 Mechanical Diagram MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-17Figure 31-10 shows the pinout for the upper right quadra

MCF548x Reference Manual, Rev. 331-18 Freescale SemiconductorFigure 31-11 shows the pinout for the lower left quadrant of the MCF5481/MCF5480 pinout f

MCF5481/5480 Mechanical Diagram MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-19Figure 31-12 shows the pinout for the lower left quadran

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-312.2.17 Power and Reference PinsThese pins provide system power,

MCF548x Reference Manual, Rev. 331-20 Freescale Semiconductor31.5 Mechanicals 388-pin PBGA Package Outline31.6 Case DrawingFigure 31-13 shows the MCF5

MCF548x Reference Manual, Rev. 3Freescale Semiconductor A-1Appendix AMCF548x Memory MapTable A-1 lists an overview of the memory map for the on-chip m

MCF548x Reference Manual, Rev. 3A-2 Freescale SemiconductorMBAR + 0x8000 –0x80FFDMA Multi-Channel DMA registersMBAR + 0x8100 –0x83FFReserved —MBAR +

MCF548x Reference Manual, Rev. 3Freescale Semiconductor A-3NOTERead and write accesses to reserved MBAR spaces will result in undefinedbehavior that

MCF548x Reference Manual, Rev. 3A-4 Freescale Semiconductor

IndexMCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-1AAcknowledge error (ACKERR) 21-16Addressing modes 3-18Associated functions 15-3BBD

MCF548x Reference Manual, Rev. 3Index-2 Freescale Semiconductorconfiguration/status (CSR) 8-11data breakpoint/mask (DBR, DBMR) 8-22extended trigger de

MCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-3port interrupt enable (EPIER) 14-4Error counters 21-30Ethernetaddress recognition 30-48

MCF548x Reference Manual, Rev. 3Index-4 Freescale Semiconductorstructure 21-19time stamp 21-28transmitcodes 21-22error status flag (TXWARN) 21-16prior

MCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-5repeated start 28-11signalsSCL 28-2SDA 28-2START 28-9STOP 28-9Instructionsarchitecture

MCF548x Reference Manual, Rev. 32-32 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Index-6 Freescale SemiconductorMechanical datacase drawing 31-20diagram 31-8pinout 31-1Memory mapsdebug 8-10DMA 24-3DS

MCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-7initiator window 2 base/translation address (PCIIW2BTAR) 19-19initiator window configur

MCF548x Reference Manual, Rev. 3Index-8 Freescale SemiconductorRRAMBAR 3-13Registerscacheaccess control (ACRn) 3-13, 5-5, 5-6, 7-22configuration (CACR

MCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-9PCI grant pin assignment (PAR_PCIBG) 15-25PCI request pin assignment (PAR_PCIBR) 15-26p

MCF548x Reference Manual, Rev. 3Index-10 Freescale Semiconductorinfrared FIR divide (PSCIRFDRn)26-26infrared MIR divide (PSCIRMDRn)26-25infrared SIR d

MCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-11USBapplication interface update (IFUR) 29-22application interrupt mask (USBAIMR) 29-17

MCF548x Reference Manual, Rev. 3Index-12 Freescale Semiconductorexecution unitsaccess 22-11AESU 22-6, 22-83AFEU 22-5, 22-67DEU 22-4, 22-72MDEU 22-6, 2

MCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-13transfer burst (TBST) 2-17, 17-4transfer size (TSIZn) 2-17, 17-4transfer start (TS) 2-

MCF548x Reference Manual, Rev. 3Index-14 Freescale Semiconductorwrite data byte mask (SDDMn)2-19write data byte mask (SDDMn) 18-3write enable (SDWE) 2

MCF548x Reference Manual, Rev. 3Freescale Semiconductor Index-15device speed (SPEEDR) 29-20dropped packet counter (DPCNT) 29-24endpoint info (EPINFO)

MCF548x Reference Manual, Rev. 3Freescale Semiconductor iPart IProcessor CorePart I is intended for system designers who need to understand the operat

MCF548x Reference Manual, Rev. 3Index-16 Freescale Semiconductor

OverviewSignal DescriptionsColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)Memory Management Unit (MMU)Floating-Point Unit (FPU)Debug SupportSyst

OverviewSignal DescriptionsColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)Memory Management Unit (MMU)Floating-Point Unit (FPU)Debug SupportSyst

MCF548x Reference Manual, Rev. 3ii Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-1Chapter 3 ColdFire CoreThis chapter provides an overview of the microprocessor core of the

MCF548x Reference Manual, Rev. 33-2 Freescale Semiconductor3.2.1 Enhanced PipelinesThe IFP prefetches instructions. The OEP decodes instructions, fetc

Features MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-3Figure 3-1. ColdFire Enhanced Pipeline3.2.1.1 Instruction Fetch Pipeline (IFP)Bec

MCF548x Reference Manual, Rev. 33-4 Freescale Semiconductor3.2.1.1.1 Branch AccelerationTo maximize the performance of conditional branch instructions

Features MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-5ColdFire microprocessor family. The MAC features a four-stage execution pipeline,

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xiContentsParagraphNumberTitlePageNumber5.2.3.9 Changes to ACRs and CACR ...

MCF548x Reference Manual, Rev. 33-6 Freescale SemiconductorThe hardware unit is optimized for real-time execution with exceptions disabled and default

Programming Model MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-7• The ASID is optionally included in the specification of the hardware b

MCF548x Reference Manual, Rev. 33-8 Freescale SemiconductorFigure 3-3. ColdFire Programming Model31 0D0 Data registersD1D2D3D4D5D6D731 0A0 Address reg

Programming Model MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-93.3.1 User Programming ModelThe user programming model, shown in Figure

MCF548x Reference Manual, Rev. 33-10 Freescale Semiconductor3.3.3 EMAC Programming Model The registers in the EMAC portion of the user programming mod

Programming Model MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-11• Eight 64-bit floating-point data registers (FP0–FP7)• One 32-bit floa

MCF548x Reference Manual, Rev. 33-12 Freescale Semiconductor3.3.5.1 Status Register (SR)The SR stores the processor status, the interrupt priority mas

Programming Model MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-133.3.5.3 Cache Control Register (CACR)The CACR controls operation of bot

MCF548x Reference Manual, Rev. 33-14 Freescale SemiconductorTable 3-4. ColdFire CPU RegistersName CPU Space (Rc) Written with MOVEC Register NameMemor

Data Format Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-153.4 Data Format SummaryTable 3-5 lists the operand data formats. Inte

MCF548x Reference Manual, Rev. 3xii Freescale SemiconductorContentsParagraphNumberTitlePageNumber6.2.3.5 Denormalized Numbers ...

MCF548x Reference Manual, Rev. 33-16 Freescale SemiconductorInstruction encodings disallow use of address registers for byte operands. When an address

Data Format Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-173.4.2 EMAC Data RepresentationThe EMAC supports the following three m

MCF548x Reference Manual, Rev. 33-18 Freescale Semiconductor3.4.2.1.1 Signed-Integer Data FormatsThe FPU supports 8-bit byte (B), 16-bit word (W), and

Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-193.6 Instruction Set SummaryThe ColdFire instruction set is a simp

MCF548x Reference Manual, Rev. 33-20 Freescale Semiconductor• Enhanced support for byte and word-sized operands through new move operations• Enhanced

Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-21Move to USP move.l Ay USP YesMove with Sign Extend mvs.{b,w} <

MCF548x Reference Manual, Rev. 33-22 Freescale Semiconductor3.6.2 Instruction Set SummaryTable 3-8 lists user-mode instructions by opcode.Save Interna

Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-23CMPCMPA<ea>y,Dx<ea>y,AxB, W, LW, LDestination – Sourc

MCF548x Reference Manual, Rev. 33-24 Freescale SemiconductorFINT <ea>y,FPxFPy,FPxFPxB,W,L,S,DDDInteger Part of Source → FPxInteger Part of FPx →

Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-25FSUB <ea>y,FPxFPy,FPxB,W,L,S,DDFPx - Source → FPxFTST <e

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xiiiContentsParagraphNumberTitlePageNumber7.8.1 Cache Line States: Invalid, Valid-Unmodified,

MCF548x Reference Manual, Rev. 33-26 Freescale SemiconductorTable 3-9 describes supervisor-mode instructions.NOT Dx L ~ Destination → DestinationOR &l

Instruction Execution Timing MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-273.7 Instruction Execution TimingThe timing data in this sect

MCF548x Reference Manual, Rev. 33-28 Freescale Semiconductor• The OEP can complete all memory accesses without memory causing any stalls. Thus, these

Instruction Execution Timing MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-29Table 3-12 lists timings for MOVE.L.Table 3-13 gives timings

MCF548x Reference Manual, Rev. 33-30 Freescale Semiconductor3.7.2 One-Operand Instruction Execution TimingTable 3-14 shows standard timings for single

Instruction Execution Timing MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-313.7.3 Two-Operand Instruction Execution TimingTable 3-15 sho

MCF548x Reference Manual, Rev. 33-32 Freescale Semiconductor3.7.4 Miscellaneous Instruction Execution TimingTable 3-16 lists timings for miscellaneous

Instruction Execution Timing MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-333.7.5 Branch Instruction Execution TimingTable 3-17 shows ge

MCF548x Reference Manual, Rev. 33-34 Freescale SemiconductorTable 3-18 shows timing for Bcc instructions.3.7.6 EMAC Instruction Execution TimesTable 3

Instruction Execution Timing MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-35Execution times for moving the contents of the ACC, ACCext[0

MCF548x Reference Manual, Rev. 3xiv Freescale SemiconductorContentsParagraphNumberTitlePageNumber8.4.5 Address Attribute Trigger Registers (AATR, AATR

MCF548x Reference Manual, Rev. 33-36 Freescale Semiconductor3.8 Exception Processing OverviewException processing for ColdFire processors is streamlin

Exception Processing Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-37If the exception is caused by an FPU instruction, the PC co

MCF548x Reference Manual, Rev. 33-38 Freescale SemiconductorColdFire processors inhibit sampling for interrupts during the first instruction of all ex

Exception Processing Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-393.8.2 Processor ExceptionsTable 3-23 describes CF4e excepti

MCF548x Reference Manual, Rev. 33-40 Freescale SemiconductorTable 3-23. Processor ExceptionsType DescriptionAccess error If the MMU is disabled, acces

Exception Processing Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-41Unimplemented line-a opcodeA line-a opcode results when bit

MCF548x Reference Manual, Rev. 33-42 Freescale Semiconductor3.9 Precise FaultsTo support a demand-paged virtual memory environment, all memory referen

Precise Faults MCF548x Reference Manual, Rev. 3Freescale Semiconductor 3-43NOTEFor access errors signaled on instruction prefetches, an access errore

MCF548x Reference Manual, Rev. 33-44 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-1Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)This chapter describes the functionality

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xvContentsParagraphNumberTitlePageNumber9.3.1.4 JTAG Device Identification Number (JTAGID) ...

MCF548x Reference Manual, Rev. 34-2 Freescale Semiconductor4.1.1 MAC OverviewThe MAC is an extension of the basic multiplier found in most microproces

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-3execution times are minimized and deterministic compared to the 2-bit/cycle a

MCF548x Reference Manual, Rev. 34-4 Freescale SemiconductorFigure 4-5. Signed and Unsigned Integer AlignmentThus, the 48-bit accumulator definition is

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-5The need to move large amounts of data presents an obstacle

MCF548x Reference Manual, Rev. 34-6 Freescale SemiconductorTable 4-1 describes MACSR fields.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R0000000000

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-7Table 4-2 summarizes the interaction of the MACSR[S/U,F/I,R

MCF548x Reference Manual, Rev. 34-8 Freescale Semiconductor4.2.1.1 Fractional Operation ModeThis section describes behavior when the fractional mode i

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-9then Result = R0.U + 1else if lsb of R0.U = 0 /* R0.L = 0x

MCF548x Reference Manual, Rev. 34-10 Freescale Semiconductormove.l d6,mask ; restore the address maskmove.l d7,macsr ; restore the macsrBy executing

EMAC Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-114.3 EMAC Instruction Set SummaryTable 4-3 summarizes EMAC un

MCF548x Reference Manual, Rev. 3xvi Freescale SemiconductorContentsParagraphNumberTitlePageNumber11.1.1 Overview ...

MCF548x Reference Manual, Rev. 34-12 Freescale SemiconductorThe mov.l instruction that stores the accumulator to an integer register (Rz) stalls until

EMAC Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-13This format can represent numbers in the range -1 < opera

MCF548x Reference Manual, Rev. 34-14 Freescale Semiconductor}else {operandY[31:0] = Ry[31:0]operandX[31:0] = Rx[31:0]}/* perform the multiply */produc

EMAC Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-15MACSR.V = 1if (MACSR.OMC == 1)then /* accumulation overflow,

MCF548x Reference Manual, Rev. 34-16 Freescale Semiconductor/* check for accumulation overflow */if (accumulationOverflow == 1)then {MACSR.PAVx = 1MAC

EMAC Instruction Set Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 4-17result[47:0] = 0xffff_ffff_ffff}/* zero-fill to 48 bits befo

MCF548x Reference Manual, Rev. 34-18 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-1Chapter 5 Memory Management Unit (MMU)This chapter describes the ColdFire virtual memory m

MCF548x Reference Manual, Rev. 35-2 Freescale Semiconductor• The address access control logic, address attribute logic, memories, and controller fun

Virtual Memory Management Architecture MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-3Figure 5-1. CF4e Processor Core Block with MMU5.2.3

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xviiContentsParagraphNumberTitlePageNumberChapter 14 Edge Port Module (EPORT)14.1 Introductio

MCF548x Reference Manual, Rev. 35-4 Freescale Semiconductor5.2.3.1 Precise FaultsThe MMU architecture performs virtual-to-physical address translation

Virtual Memory Management Architecture MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-5more bits than the in-page address, one or more of

MCF548x Reference Manual, Rev. 35-6 Freescale Semiconductor5.2.3.10 ACR Address ImprovementsACRs provide a 16-Mbyte address window. For a given reques

Debugging in a Virtual Environment MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-75.2.3.11 Supervisor ProtectionEach instruction or data

MCF548x Reference Manual, Rev. 35-8 Freescale SemiconductorIn addition, the following two privileged M68000 family instructions to load/store the USP

MMU Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-95.5 MMU DefinitionThe ColdFire MMU provides a virtual address, demand-paged

MCF548x Reference Manual, Rev. 35-10 Freescale Semiconductor• If virtual mode is enabled, any normal mode access that does not hit in the MMUBAR, RAMB

MMU Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-115.5.3.2 MMU Memory MapMMUBAR holds the base address for the 64-Kbyte MMU m

MCF548x Reference Manual, Rev. 35-12 Freescale SemiconductorTable 5-5 describes MMUCR fields. 5.5.3.4 MMU Operation Register (MMUOR)Figure 5-5 shows t

MMU Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-13Table 5-6 describes MMUOR fields.31 30 29 28 27 26 25 24 23 22 21 20 19 18

MCF548x Reference Manual, Rev. 3xviii Freescale SemiconductorContentsParagraphNumberTitlePageNumber15.4 Functional Description ...

MCF548x Reference Manual, Rev. 35-14 Freescale Semiconductor5.5.3.5 MMU Status Register (MMUSR)MMUSR, Figure 5-6, is updated on all data access faults

MMU Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-155.5.3.6 MMU Fault, Test, or TLB Address Register (MMUAR)The MMUAR format,

MCF548x Reference Manual, Rev. 35-16 Freescale Semiconductor5.5.3.7 MMU Read/Write Tag and Data Entry Registers (MMUTR and MMUDR)Each TLB entry consis

MMU Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-17MMUDR, Figure 5-9, contains the physical address, page size, cache mode fi

MCF548x Reference Manual, Rev. 35-18 Freescale Semiconductor5.5.4 MMU TLBEach TLB entry consists of two 32-bit fields. The first is the TLB tag entry,

MMU Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-195.5.5 MMU OperationThe processor sends instruction fetch requests and data

MCF548x Reference Manual, Rev. 35-20 Freescale SemiconductorFigure 5-10 shows more details of the MMU structure. The TLB is accessed at the beginning

MMU Implementation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-21When MMUAR is used for a TLB address, bits FA[5–0] also have this addr

MCF548x Reference Manual, Rev. 35-22 Freescale SemiconductorBinary state bits are updated on all TLB write (load) operations, as well as normal ITLB a

MMU Instructions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 5-23Figure 5-11. Version 4 ColdFire MMU Harvard TLB 5.7 MMU InstructionsThe

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xixContentsParagraphNumberTitlePageNumber17.5.1.2 Global Chip-Select Operation ...

MCF548x Reference Manual, Rev. 35-24 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-1Chapter 6 Floating-Point Unit (FPU)6.1 IntroductionThis chapter describes instructions imp

MCF548x Reference Manual, Rev. 36-2 Freescale SemiconductorTable 6-2 describes addressing modes and syntax for floating-point instructions.& Logic

Operand Data Formats and Types MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-36.2 Operand Data Formats and TypesThe FPU supports signed b

MCF548x Reference Manual, Rev. 36-4 Freescale Semiconductoryields a signed, two’s complement power of two. This represents the magnitude of a normaliz

Operand Data Formats and Types MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-56.2.3.4 Not-A-NumberWhen created by the FPU, NANs represent

MCF548x Reference Manual, Rev. 36-6 Freescale SemiconductorBiased exponent (e) 8 11Fraction (f) 23 52Tota l 32 64Interpretation of SignPositive fracti

Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-76.3 Register DefinitionThe programmer’s model for the FPU consists of

MCF548x Reference Manual, Rev. 36-8 Freescale SemiconductorThe user can read or write to FPCR using FMOVE or FRESTORE. A processor reset or a restore

Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-96.3.3 Floating-Point Status Register (FPSR) The FPSR, Figure 6-10, con

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MCF548x Reference Manual, Rev. 3xx Freescale SemiconductorContentsParagraphNumberTitlePageNumber18.3.13 SDR SDRAM Data Strobe (SDRDQS) ...

MCF548x Reference Manual, Rev. 36-10 Freescale SemiconductorFor AEXC[OVFL], AEXC[DZ], and AEXC[INEX], the next value is determined by ORing the curren

Floating-Point Computational Accuracy MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-11For FPU instructions that can generate exception tr

MCF548x Reference Manual, Rev. 36-12 Freescale Semiconductordouble-precision format. If the destination is a memory location or an integer data regist

Floating-Point Computational Accuracy MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-13Figure 6-12. Rounding Algorithm FlowchartThe 3 addi

MCF548x Reference Manual, Rev. 36-14 Freescale SemiconductorThe lsb of the rounded result does not increment even though the guard bit is set in the i

Floating-Point Post-Processing MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-15rounding precision and mode. After rounding, the inexact b

MCF548x Reference Manual, Rev. 36-16 Freescale Semiconductorunordered condition is present when the conditional test is attempted (IEEE nonaware tests

Floating-Point Exceptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-176.6 Floating-Point ExceptionsThis section describes floating-po

MCF548x Reference Manual, Rev. 36-18 Freescale SemiconductorIn addition to these vectors, attempting to execute a FRESTORE instruction with a unsuppor

Floating-Point Exceptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-19A floating-point arithmetic exception becomes pending when the

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxiContentsParagraphNumberTitlePageNumber18.8.9 Perform Two Refresh Cycles ...

MCF548x Reference Manual, Rev. 36-20 Freescale Semiconductor6.6.1.2 Input Not-A-Number (INAN)The INAN exception is a mechanism for handling a user-def

Floating-Point Exceptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-216.6.1.4 Operand Error (OPERR)The operand error exception encomp

MCF548x Reference Manual, Rev. 36-22 Freescale Semiconductor6.6.1.6 Underflow (UNFL)An underflow exception occurs when the intermediate result of an a

Floating-Point Exceptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-236.6.1.8 Inexact Result (INEX)An INEX exception condition exists

MCF548x Reference Manual, Rev. 36-24 Freescale SemiconductorNote that if no intervention is needed, instead of FSAVE, the handler can simply clear the

Instructions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-25Normally, an exception handler executes FSAVE, processes the exception, clea

MCF548x Reference Manual, Rev. 36-26 Freescale SemiconductorTable 6-24 defines the terminology used in Table 6-23. FMOVE 1111001000 ea modeea reg 0 r/

Instructions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-276.7.2 Floating-Point Instruction Execution TimingTable 6-25 shows the ColdFi

MCF548x Reference Manual, Rev. 36-28 Freescale SemiconductorThe ColdFire architecture supports concurrent execution of integer and floating-point inst

Instructions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 6-29Some differences affect function activation and return. M68000 subroutines t

MCF548x Reference Manual, Rev. 3xxii Freescale SemiconductorContentsParagraphNumberTitlePageNumber19.3.2.2 Target Base Address Translation Register 0

MCF548x Reference Manual, Rev. 36-30 Freescale Semiconductorvalues be moved into a table of constants that can be referenced using PC-relative address

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-1Chapter 7 Local Memory This chapter describes the MCF548x implementation of the ColdFire V

MCF548x Reference Manual, Rev. 37-2 Freescale Semiconductor• Physical location on the processor’s high-speed local bus with a user-programmed connecti

SRAM Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-3 RAMBARn fields are described in detail in Table 7-1.31 30 29 28

MCF548x Reference Manual, Rev. 37-4 Freescale SemiconductorThe mapping of a given access into the SRAM uses the following algorithm to determine if th

SRAM Initialization MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-53. After the data is loaded into the SRAM, it may be appropriate to re

MCF548x Reference Manual, Rev. 37-6 Freescale Semiconductor; +20 destinationOffset; +24 bytesToMovemove.l RAMBASE+RAMFLAGS,a0 ;define RAMBAR0 conten

Cache Organization MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-7The MCF548x processor’s Harvard memory structure includes a 32-Kbyte da

MCF548x Reference Manual, Rev. 37-8 Freescale SemiconductorFigure 7-3. Data Cache Organization and Line FormatA set is a group of four lines (one from

Cache Organization MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-9Figure 7-4. Data Cache—A: at Reset, B: after Invalidation, C and D: Loa

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxiiiContentsParagraphNumberTitlePageNumber19.4.6.6 PCI Commands ...

MCF548x Reference Manual, Rev. 37-10 Freescale Semiconductor7.9 Cache OperationFigure 7-5 shows the general flow of a caching operation using the 32-K

Cache Operation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-11pseudo-round-robin replacement algorithm to choose the line to be dealloc

MCF548x Reference Manual, Rev. 37-12 Freescale SemiconductorValid cache entries that match during cache-inhibited address accesses are neither pushed

Cache Operation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-137.9.1.1.2 Copyback Mode (Data Cache Only)Copyback regions are typically u

MCF548x Reference Manual, Rev. 37-14 Freescale Semiconductoran exception aborts the instruction and the data may be accessed again when the instructio

Cache Operation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-157.9.2.3 Read HitOn a read hit, the cache provides the data to the process

MCF548x Reference Manual, Rev. 37-16 Freescale Semiconductor7.9.4.2 Cache PushesCache pushes occur for line replacement and as required for the execut

Cache Operation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-177.9.5 Cache LockingWays 0 and 1 of the data cache can be locked by settin

MCF548x Reference Manual, Rev. 37-18 Freescale SemiconductorFigure 7-7. Data Cache LockingA: Ways 0 and 1 are filled. Ways 2 and 3 are invalid.B: CACR

Cache Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-197.10 Cache Register DefinitionThis section describes the MCF548

MCF548x Reference Manual, Rev. 3xxiv Freescale SemiconductorContentsParagraphNumberTitlePageNumber20.6 Interrupts ...

MCF548x Reference Manual, Rev. 37-20 Freescale Semiconductor28 DDPI Disable CPUSHL invalidation.0 Normal operation. A CPUSHL instruction causes the se

Cache Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-2113 DNFB Default cache-inhibited fill buffer0 Fill buffer does n

MCF548x Reference Manual, Rev. 37-22 Freescale Semiconductor7.10.2 Access Control Registers (ACR0–ACR3)The ACRs, Figure 7-9, assign control attributes

Cache Management MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-237.11 Cache ManagementThe cache can be enabled and configured by using a

MCF548x Reference Manual, Rev. 37-24 Freescale SemiconductorThe contents of An used with CPUSHL specify cache row and line indexes. This differs from

Cache Management MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-25dataCacheLoadAndLock:move.l #0xa3080800,d0; enable and invalidate data c

MCF548x Reference Manual, Rev. 37-26 Freescale Semiconductor7.12 Cache Operation SummaryThis section gives operational details for the cache and prese

Cache Operation Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-277.12.2 Data Cache State TransitionsUsing the V and M bits, the da

MCF548x Reference Manual, Rev. 37-28 Freescale Semiconductor The following tables present the same information as Table 7-7, organized by the current

Cache Operation Summary MCF548x Reference Manual, Rev. 3Freescale Semiconductor 7-29In Table 7-9 the current state is valid.Table 7-8. Data Cache Lin

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxvContentsParagraphNumberTitlePageNumber21.4.7 CAN Protocol Related Frames ...

MCF548x Reference Manual, Rev. 37-30 Freescale SemiconductorIn Table 7-10 the current state is modified.7.13 Cache Initialization CodeThe following ex

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-1Chapter 8 Debug Support8.1 IntroductionThis chapter describes the Revision D enhanced hard

MCF548x Reference Manual, Rev. 38-2 Freescale Semiconductorgenerations of ColdFire cores. For Revision A, CSR[HRL] is 0. See Section 8.4.2, “Configura

Signal Descriptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-3Figure 8-2 shows PSTCLK timing with respect to PSTDDATA.Figure 8-2. PS

MCF548x Reference Manual, Rev. 38-4 Freescale Semiconductoroutput for the processor’s sequential execution of single-cycle instructions (A, B, C, D...

Real-Time Trace Support MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-5NOTEA PST marker and its data display are sent contiguously. Excep

MCF548x Reference Manual, Rev. 38-6 Freescale Semiconductor8.3.1 Begin Execution of Taken Branch (PST = 0x5)PST is 0x5 when a taken branch is executed

Real-Time Trace Support MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-7The simplest example of a branch instruction using a variant addre

MCF548x Reference Manual, Rev. 38-8 Freescale Semiconductor8.3.3 Processor Halted (PST = 0xF)PST is 0xF when the processor is halted (see Section 8.5.

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-98.4 Memory Map/Register DefinitionIn addition to the existi

MCF548x Reference Manual, Rev. 3xxvi Freescale SemiconductorContentsParagraphNumberTitlePageNumber22.6.4.8 Master Error Address Register (MEAR) ...

MCF548x Reference Manual, Rev. 38-10 Freescale SemiconductorThe registers in Table 8-7 are accessed through the BDM port by BDM commands, WDMREG and R

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-11to guarantee that all accesses to these resources are seri

MCF548x Reference Manual, Rev. 38-12 Freescale SemiconductorTable 8-8 describes CSR fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R BSTAT FOF

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-1318 BKD Breakpoint disable. Used to disable the normal BKPT

MCF548x Reference Manual, Rev. 38-14 Freescale Semiconductor8.4.3 PC Breakpoint ASID Control Register (PBAC)The PBAC configures the breakpoint qualifi

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-15qualification. Reset clears these fields, disabling qualif

MCF548x Reference Manual, Rev. 38-16 Freescale Semiconductor8.4.5 Address Attribute Trigger Registers (AATR, AATR1)The AATR and AATR1, Figure 8-9, def

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-178.4.6 Trigger Definition Register (TDR)The TDR, shown in T

MCF548x Reference Manual, Rev. 38-18 Freescale Semiconductortaken under the defined conditions. Breakpoint logic may be configured as one- or two-leve

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-1928 EDLW2 Data enable bit: Data longword. Entire processor’

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxviiContentsParagraphNumberTitlePageNumber22.13.1.2 Descriptor Length and Pointer Fields ...

MCF548x Reference Manual, Rev. 38-20 Freescale Semiconductor8.4.7 Program Counter Breakpoint and Mask Registers (PBRn, PBMR)Each PC breakpoint registe

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-21Figure 8-12 shows PBMR. PBMR is accessible in supervisor m

MCF548x Reference Manual, Rev. 38-22 Freescale SemiconductorTable 8-15 describes ABLR and ABLR1 fields. Table 8-16 describes ABHR and ABHR1 fields.8.4

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-23Table 8-17 describes DBRn fields.DBMR and DBMR1 are access

MCF548x Reference Manual, Rev. 38-24 Freescale SemiconductorDBRs support both aligned and misaligned references. Table 8-19 shows relationships betwee

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-258.4.11 Extended Trigger Definition Register (XTDR)The XTDR

MCF548x Reference Manual, Rev. 38-26 Freescale SemiconductorTable 8-21 describes XTDR fields.Table 8-21. XTDR Field DescriptionsBits Name Description3

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-278.4.11.1 Resulting Set of Possible Trigger CombinationsThe

MCF548x Reference Manual, Rev. 38-28 Freescale Semiconductorthen if (PC_breakpoint|| Address1_breakpoint{&& Data1_breakpoint})if (Address1_bre

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-294. The assertion of the BKPT input is treated as a pseudo-int

MCF548x Reference Manual, Rev. 3xxviii Freescale SemiconductorContentsParagraphNumberTitlePageNumber23.2.1.3 Test Mode Select/Breakpoint (TMS/BKPT) ..

MCF548x Reference Manual, Rev. 38-30 Freescale Semiconductor8.5.2 BDM Serial InterfaceWhen the CPU is halted and PSTDDATA reflects the halt status, th

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-31.Table 8-22 describes receive BDM packet fields. 8.5.2.2 Tran

MCF548x Reference Manual, Rev. 38-32 Freescale SemiconductorUnassigned command opcodes are reserved by Freescale. All unused command formats within an

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-338.5.3.1 ColdFire BDM Command FormatAll ColdFire Family BDM co

MCF548x Reference Manual, Rev. 38-34 Freescale Semiconductorsends to the debug module; the bottom half indicates the debug module’s response to the pr

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-358.5.3.3 Command Set DescriptionsThe following sections descri

MCF548x Reference Manual, Rev. 38-36 Freescale SemiconductorCommand Format:Command SequenceFigure 8-26. WAREG/WDREG Command SequenceOperand Data Longw

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-37Command Sequence:Figure 8-28. READ Command SequenceOperand Da

MCF548x Reference Manual, Rev. 38-38 Freescale SemiconductorResult Data Word results return 16 bits of data; longword results return 32. Bytes are ret

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-39Command Sequence:Figure 8-30. WRITE Command SequenceOperand D

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxixContentsParagraphNumberTitlePageNumber24.2.1 DREQ[1:0] ...

MCF548x Reference Manual, Rev. 38-40 Freescale SemiconductorNOTEDUMP does not check for a valid address; it is a valid command only whenpreceded by NO

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-41Result Data: Requested data is returned as either a word or l

MCF548x Reference Manual, Rev. 38-42 Freescale SemiconductorCommand Sequence:Figure 8-34. FILL Command SequenceOperand Data: A single operand is data

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-43Result Data: The command-complete response (0xFFFF) is return

MCF548x Reference Manual, Rev. 38-44 Freescale SemiconductorCommand Sequence:Figure 8-40. SYNC_PC Command SequenceOperand Data: NoneResult Data: Comma

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-45Figure 8-42. FORCE_TA Command SequenceOperand Data: NoneResu

MCF548x Reference Manual, Rev. 38-46 Freescale SemiconductorTable 8-26. ColdFire CPU Control Register MapName CPU Space (Rc) Register NameMemory Mana

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-478.5.3.3.12 BDM Accesses of the Stack Pointer Registers (A7: S

MCF548x Reference Manual, Rev. 38-48 Freescale SemiconductorLikewise, to write an accumulator register, the following BDM sequence is needed:BdmWriteA

Background Debug Mode (BDM) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-49Command Sequence:Figure 8-46. WCREG Command SequenceOperand D

OverviewSignal DescriptionsColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)Memory Management Unit (MMU)Floating-Point Unit (FPU)Debug SupportSyst

MCF548x Reference Manual, Rev. 3xxx Freescale SemiconductorContentsParagraphNumberTitlePageNumber24.4.8.1 LURC Features ...

MCF548x Reference Manual, Rev. 38-50 Freescale SemiconductorTable 8-27 shows the definition of DRc encoding.Command Sequence:Figure 8-48. RDMREG Comma

Real-Time Debug Support MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-51Figure 8-50. WDMREG Command SequenceOperand Data: Longword data i

MCF548x Reference Manual, Rev. 38-52 Freescale SemiconductorBDM instructions use the appropriate registers to load and configure breakpoints. As the s

Real-Time Debug Support MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-534. It executes an RTE instruction when the exception handler fini

MCF548x Reference Manual, Rev. 38-54 Freescale Semiconductor• Read/write control registersFor BDM commands that access memory, the debug module reques

Debug C Definition of PSTDDATA Outputs MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-55andi.l #<data>,Dx PSTDDATA = 0x1asl.l {Dy,#&

MCF548x Reference Manual, Rev. 38-56 Freescale Semiconductorextb.l Dx PSTDDATA = 0x1illegal PSTDDATA = 0x11jmp <ea>y PSTDDATA = 0x5, {[0x9AB], t

Debug C Definition of PSTDDATA Outputs MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-57ori.l #<data>,Dx PSTDDATA = 0x1pea.l <ea&

MCF548x Reference Manual, Rev. 38-58 Freescale SemiconductorTable 8-31 shows the PSTDDATA specification for multiply-accumulate instructions.1During n

Debug C Definition of PSTDDATA Outputs MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-59Table 8-32 shows the PSTDDATA specification for fl

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxxiContentsParagraphNumberTitlePageNumber26.1.1 Block Diagram ...

MCF548x Reference Manual, Rev. 38-60 Freescale SemiconductorDepending on the size of any external memory operand specified by the f<op>.fmt fiel

ColdFire Debug History MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-61The move-to-SR and RTE instructions include an optional PSTDDATA =

MCF548x Reference Manual, Rev. 38-62 Freescale SemiconductorThe data_breakpoint can be included as an optional part of an address breakpoint.The ColdF

Freescale-Recommended BDM Pinout MCF548x Reference Manual, Rev. 3Freescale Semiconductor 8-63Additionally, the execution of the debug interrupt servi

MCF548x Reference Manual, Rev. 38-64 Freescale SemiconductorFigure 8-51. Recommended BDM Connector1357911131517192123252468101214161820222426Developer

MCF548x Reference Manual, Rev. 3Freescale Semiconductor iPart IISystem Integration UnitPart II describes the system integration unit, which provides o

MCF548x Reference Manual, Rev. 3ii Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 9-1Chapter 9 System Integration Unit (SIU)9.1 IntroductionThe system integration unit (SIU) o

MCF548x Reference Manual, Rev. 39-2 Freescale Semiconductor9.3.1 Module Base Address Register (MBAR)The supervisor-level MBAR, Figure 9-1, specifies t

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 9-39.3.1.1 System Breakpoint Control Register (SBCR)The System

MCF548x Reference Manual, Rev. 3xxxii Freescale SemiconductorContentsParagraphNumberTitlePageNumber26.3.3.28 Rx and Tx FIFO Last Read Frame Pointer (P

MCF548x Reference Manual, Rev. 39-4 Freescale Semiconductor9.3.1.2 SEC Sequential Access Control Register (SECSACR)This register is used to control b

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 9-59.3.1.3 Reset Status Register (RSR)RSR allows the software,

MCF548x Reference Manual, Rev. 39-6 Freescale SemiconductorTable 9-5. JTAGID Field DescriptionsBits Name Description31–0 JTAGID The JTAG Identificati

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-1Chapter 10 Internal Clocks and Bus Architecture10.1 IntroductionThis chapter describes th

MCF548x Reference Manual, Rev. 310-2 Freescale Semiconductor10.1.2 Clocking OverviewThe MCF548x requires a clock generated externally to be input to t

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-3• CommBus — The data transfer interface between the multichannel DMA and eac

MCF548x Reference Manual, Rev. 310-4 Freescale SemiconductorFigure 10-3. Address and Data TenuresThe following outlines the basic functions of each of

PLL MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-510.2 PLL10.2.1 PLL Memory Map/Register Descriptions 10.2.2 System PLL Control Registe

MCF548x Reference Manual, Rev. 310-6 Freescale Semiconductor10.3 XL Bus ArbiterThe XL bus arbiter handles bus arbitration between XL bus masters.10.3.

XL Bus Arbiter MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-7algorithm (LRU). Once a requesting master is identified as having priority

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxxiiiContentsParagraphNumberTitlePageNumber26.7.2.5 SIR Mode ...

MCF548x Reference Manual, Rev. 310-8 Freescale Semiconductor10.3.2.3 Watchdog Functions10.3.2.3.1 Timer FunctionsThere are three watchdog timers: addr

XL Bus Arbiter MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-910.3.3.1 Arbiter Configuration Register (XARB_CFG)The arbiter configuratio

MCF548x Reference Manual, Rev. 310-10 Freescale Semiconductor10.3.3.2 Arbiter Version Register (XARB_VER)4 — Reserved, should be cleared.3 BA Bus Acti

XL Bus Arbiter MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-1110.3.3.3 Arbiter Status Register (XARB_SR)The arbiter status register ind

MCF548x Reference Manual, Rev. 310-12 Freescale Semiconductorto determine the state of the arbiter. It is possible that multiple conditions exist that

XL Bus Arbiter MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-1310.3.3.5 Arbiter Address Capture Register (XARB_ADRCAP)The arbiter addres

MCF548x Reference Manual, Rev. 310-14 Freescale Semiconductor10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO)31 30 29 28 27 26 25 24 23

XL Bus Arbiter MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-1510.3.3.8 Arbiter Data Tenure Time Out Register (XARB_DATTO)Table 10-11. X

MCF548x Reference Manual, Rev. 310-16 Freescale Semiconductor10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO)10.3.3.10 Arbiter Master Prio

XL Bus Arbiter MCF548x Reference Manual, Rev. 3Freescale Semiconductor 10-17When enabled, the software programmable value in the arbiter master prior

MCF548x Reference Manual, Rev. 3xxxiv Freescale SemiconductorContentsParagraphNumberTitlePageNumber27.7.2.4 Tx FIFO Buffering Mechanism ...

MCF548x Reference Manual, Rev. 310-18 Freescale SemiconductorTable 10-16. XARB_PRI Field DescriptionsBits Name Description31–15 — Reserved, should be

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 11-1Chapter 11 General Purpose Timers (GPT)11.1 IntroductionThis chapter describes the operat

MCF548x Reference Manual, Rev. 311-2 Freescale Semiconductor6. Watchdog Timer—This is a special CPU timer mode, available only on GPT0. The user must

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 11-311.3.1 GPT Enable and Mode Select Register (GMSn)31 30 29

MCF548x Reference Manual, Rev. 311-4 Freescale Semiconductor15 WDEN Watchdog enable. Enables watchdog operation. A timer expiration causes an internal

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 11-511.3.2 GPT Counter Input Register (GCIRn)8 IEN Interrupt e

MCF548x Reference Manual, Rev. 311-6 Freescale Semiconductor11.3.3 GPT PWM Configuration Register (GPWMn)Table 11-3. GCIRn Field DescriptionsBits Name

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 11-711.3.4 GPT Status Register (GSRn)7–1 — Reserved. Should be

MCF548x Reference Manual, Rev. 311-8 Freescale Semiconductor11.4 Functional Description11.4.1 Timer Configuration MethodUse the following method to co

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 12-1Chapter 12 Slice Timers (SLT)12.1 IntroductionThis chapter explains the operation of the

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxxvContentsParagraphNumberTitlePageNumber28.3.2.1 I2C Address Register (I2ADR) ...

MCF548x Reference Manual, Rev. 312-2 Freescale Semiconductor12.2.1 SLT Terminal Count Register (STCNTn)12.2.2 SLT Control Register (SCRn)31 30 29 28 2

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 12-312.2.3 SLT Timer Count Register (SCNTn)Table 12-3. SCRn Fi

MCF548x Reference Manual, Rev. 312-4 Freescale Semiconductor12.2.4 SLT Status Register (SSRn)31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R000000BES

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 13-1Chapter 13 Interrupt Controller13.1 IntroductionThis section details the functionality fo

MCF548x Reference Manual, Rev. 313-2 Freescale Semiconductorand status register data, along with the 32-bit program counter value of the instruction t

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 13-38 fully-programmable interrupt sources are mapped into a single interrupt le

MCF548x Reference Manual, Rev. 313-4 Freescale Semiconductorexplicitly cleared in the interrupt service routine. This design provides unique vector ca

Memory Map/Register Descriptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 13-513.2.1 Register Descriptions13.2.1.1 Interrupt Pending R

MCF548x Reference Manual, Rev. 313-6 Freescale SemiconductorThe IPR is a read-only register, so any attempted write to this register is ignored. Bit 0

Memory Map/Register Descriptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 13-713.2.1.2 Interrupt Mask Register (IMRH, IMRL)The IMRH an

MCF548x Reference Manual, Rev. 3xxxvi Freescale SemiconductorContentsParagraphNumberTitlePageNumber29.2.2.3 USB Descriptor RAM Control Register (DRAMC

MCF548x Reference Manual, Rev. 313-8 Freescale Semiconductor13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL)The INTFRCH and INTFRCL registers are

Memory Map/Register Descriptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 13-9. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R INTFR

MCF548x Reference Manual, Rev. 313-10 Freescale Semiconductor13.2.1.4 Interrupt Request Level Register (IRLR)This 7-bit register is updated each machi

Memory Map/Register Descriptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 13-1113.2.1.6 Interrupt Control Registers 1–63 (ICRn)Each IC

MCF548x Reference Manual, Rev. 313-12 Freescale Semiconductor13.2.1.6.1 Interrupt SourcesTable 13-12 lists the interrupt sources for each interrupt re

Memory Map/Register Descriptions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 13-1313.2.1.7 Software and Level n IACK Registers (SWIACKR,

MCF548x Reference Manual, Rev. 313-14 Freescale Semiconductordetermines the highest priority within the level, and then responds with the unique vecto

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 14-1Chapter 14 Edge Port Module (EPORT) 14.1 IntroductionThe edge port module (EPORT) has sev

MCF548x Reference Manual, Rev. 314-2 Freescale SemiconductorNOTEThe GPIO functionality of the external interrupt pins is controlled by theEPORT module

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 14-314.3.2.1 EPORT Pin Assignment Register (EPPAR)14.3.2.2 EPO

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxxviiContentsParagraphNumberTitlePageNumber29.2.5.6 USB Endpoint n FIFO Status Register (EPnF

MCF548x Reference Manual, Rev. 314-4 Freescale Semiconductor14.3.2.3 Edge Port Interrupt Enable Register (EPIER)14.3.2.4 Edge Port Data Register (EPDR

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 14-514.3.2.5 Edge Port Pin Data Register (EPPDR)14.3.2.6 Edge

MCF548x Reference Manual, Rev. 314-6 Freescale SemiconductorTable 14-7. EPFR Field DescriptionsBits Name Description7–1 EPFn Edge port flag bits. When

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-1Chapter 15 GPIO15.1 IntroductionMany of the MCF548x pins whose primary function is to ser

MCF548x Reference Manual, Rev. 315-2 Freescale SemiconductorFigure 15-1. MCF548x GPIO Module Block Diagram15.1.1 OverviewThe MCF548x GPIO module contr

External Pin Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-3• External DMA request and acknowledge (DMA)• PCI bus access (PC

MCF548x Reference Manual, Rev. 315-4 Freescale SemiconductorDACK0PDMA2 TOUT0 — DMA acknowledge 0 / Port DMA2 / GP timer output 0DREQ1 PDMA1 TIN1 IRQ1

External Pin Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-5FEC1MDC — SCL CANTX0 Ethernet Controller 1 management data clock

MCF548x Reference Manual, Rev. 315-6 Freescale SemiconductorRefer to the signals chapter of the MCF548x chip specification for more detailed descripti

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-7It should be noted from Table 15-1 that there are several

MCF548x Reference Manual, Rev. 3xxxviii Freescale SemiconductorContentsParagraphNumberTitlePageNumber30.1.5.4 Internal Loopback ...

MCF548x Reference Manual, Rev. 315-8 Freescale Semiconductor15.3.2 Register Descriptions15.3.2.1 Port x Output Data Registers (PODR_x)The PODR registe

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-9Most PODR_x registers have full 8-bit implementations, as

MCF548x Reference Manual, Rev. 315-10 Freescale Semiconductor15.3.2.1.3 5-Bit PODR_x RegistersThe 5-bit PODR_x registers are the output data registers

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-1115.3.2.1.5 FBCS Register (PODR_FBCS)The 5-bit PODR_FBCS r

MCF548x Reference Manual, Rev. 315-12 Freescale SemiconductorMost PDDR_x registers have a full 8-bit implementation, as shown in Figure 15-7. The rema

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-1315.3.2.2.3 5-Bit PDDR_x RegistersThe 5-bit PDDR_x registe

MCF548x Reference Manual, Rev. 315-14 Freescale Semiconductor15.3.2.2.5 FBCS Register (PDDR_FBCS)The 5-bit PDDR_FBCS register is for data direction of

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-15Most PPDSDR_x registers have a full 8-bit implementation,

MCF548x Reference Manual, Rev. 315-16 Freescale Semiconductor15.3.2.3.3 5-Bit PPDSDR_x RegistersThe 5-bit PPDSDR_x registers are the pin data and set

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-1715.3.2.3.4 4-Bit PPDSDR_x RegistersThe 4-bit PPDSDR_x reg

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xxxixContentsParagraphNumberTitlePageNumber30.3.3.24 FEC Receive FIFO Read Pointer Register (F

MCF548x Reference Manual, Rev. 315-18 Freescale Semiconductor15.3.2.4 Port x Clear Output Data Registers (PCLRR_x)Writing 0s to a PCLRR_x register cle

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-1915.3.2.4.1 7-Bit PCLRR_x RegisterThe 7-bit PCLRR_DSPI reg

MCF548x Reference Manual, Rev. 315-20 Freescale Semiconductor15.3.2.4.3 4-Bit PCLRR_x RegistersThe 4-bit PCLRR_x registers are the clear output data r

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-2115.3.2.5 Port x Pin Assignment Registers (PAR_x)The PAR_x

MCF548x Reference Manual, Rev. 315-22 Freescale Semiconductor15.3.2.6 FlexBus Chip Select Pin Assignment Register (PAR_FBCS)The PAR_FBCS register cont

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-2315.3.2.7 DMA Pin Assignment Register (PAR_DMA)The PAR_DMA

MCF548x Reference Manual, Rev. 315-24 Freescale Semiconductor151413 1211109876543210RPAR_E07PAR _E0MIIPAR _E0MDIOPAR _E0MDCPAR _E17PAR _E1MIIPAR_E1MDI

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-2515.3.2.9 PCI Grant Pin Assignment Register (PAR_PCIBG)The

MCF548x Reference Manual, Rev. 315-26 Freescale Semiconductor15.3.2.10 PCI Request Pin Assignment Register (PAR_PCIBR)The PAR_PCIBR controls the funct

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-2715.3.2.11 PSC3 Pin Assignment Register (PAR_PSC3)The PAR_

OverviewSignal DescriptionsColdFire CoreEnhanced Multiply-Accumulate Unit (EMAC)Memory Management Unit (MMU)Floating-Point Unit (FPU)Debug SupportSyst

MCF548x Reference Manual, Rev. 3xl Freescale SemiconductorContentsParagraphNumberTitlePageNumber31.3.2 MCF5483/5482 Mechanical Diagram ...

MCF548x Reference Manual, Rev. 315-28 Freescale Semiconductor15.3.2.12 PSC2 Pin Assignment Register (PAR_PSC2)The PAR_PSC2 register controls the funct

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-2915.3.2.14 PSC0 Pin Assignment Register (PAR_PSC0)The PAR_

MCF548x Reference Manual, Rev. 315-30 Freescale Semiconductor15.3.2.15 DSPI Pin Assignment Register (PAR_DSPI)The PAR_DSPI register controls the funct

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-3115.3.2.16 General Purpose Timer Pin Assignment Register (

MCF548x Reference Manual, Rev. 315-32 Freescale SemiconductorNOTEExplicit pin function assignment capability for the TIN1, TOUT1, TIN0,and TOUT0 pins

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 15-33(PPDSDR_x) to monitor and control the state of its pins. Data wri

MCF548x Reference Manual, Rev. 315-34 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor iPart IIIOn-Chip IntegrationPart III describes on-chip integration for the MCF548x device. It

MCF548x Reference Manual, Rev. 3ii Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 16-1Chapter 16 32-Kbyte System SRAM16.1 IntroductionThis chapter explains the operation of th

MCF548x Reference Manual, Rev. 3Freescale Semiconductor xliAbout This BookThe primary objective of this reference manual is to define the functionalit

MCF548x Reference Manual, Rev. 316-2 Freescale SemiconductorThe system SRAM contents always reside at MBAR + 0x0001 0000; therefore, it can be relocat

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 16-316.2.1 System SRAM Configuration Register (SSCR)This regis

MCF548x Reference Manual, Rev. 316-4 Freescale Semiconductor16.2.2 Transfer Count Configuration Register (TCCR) This register is used to configure the

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 16-516.2.3 Transfer Count Configuration Register—DMA Read Chan

MCF548x Reference Manual, Rev. 316-6 Freescale Semiconductor16.2.4 Transfer Count Configuration Register—DMA Write Channel (TCCRDW)This register is us

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 16-716.2.5 Transfer Count Configuration Register—SEC (TCCRSEC)

MCF548x Reference Manual, Rev. 316-8 Freescale Semiconductor16.3 Functional DescriptionThe system SRAM decodes the addresses for all four banks to det

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-1Chapter 17 FlexBus17.1 IntroductionThis chapter describes data transfer operations, error

MCF548x Reference Manual, Rev. 317-2 Freescale Semiconductor17.2 Byte LanesFigure 17-1 shows the byte lanes that external memory should be connected t

External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-3Figure 17-2. Multiplexed FlexBus Implementation17.4 External SignalsThis

MCF548x Reference Manual, Rev. 3xlii Freescale Semiconductor— Chapter 7, “Local Memory,” describes the MCF548x implementation of the ColdFire V4e loca

MCF548x Reference Manual, Rev. 317-4 Freescale Semiconductor17.4.1 Chip-Select (FBCS[5:0])The chip-select signal indicates which device is being selec

External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-5For aligned transfers larger than the port size, TSIZ[1:0] behaves as fo

MCF548x Reference Manual, Rev. 317-6 Freescale Semiconductor17.5 Chip-Select OperationEach chip-select has a dedicated set of the following registers

Chip-Select Operation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-717.5.2 Chip-Select RegistersThe following tables describe in detail

MCF548x Reference Manual, Rev. 317-8 Freescale Semiconductor1 The access column indicates whether the corresponding register allows both read/write fu

Chip-Select Operation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-917.5.2.2 Chip-Select Mask Registers (CSMR0–CSMR5)CSMRn, Figure 17-4

MCF548x Reference Manual, Rev. 317-10 Freescale Semiconductor17.5.2.3 Chip-Select Control Registers (CSCR0–CSCR5)Each CSCRn, Figure 17-5, controls the

Chip-Select Operation MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-1119–18 RDAH Read Address Hold or (Deselect). This field controls th

MCF548x Reference Manual, Rev. 317-12 Freescale Semiconductor17.6 Functional Description17.6.1 Data Transfer OperationData transfers between the MCF54

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-13Figure 17-6. Connections for External Memory Port Sizes17.6.3 Add

Suggested ReadingMCF548x Reference Manual, Rev. 3Freescale Semiconductor xliii— Chapter 21, “FlexCAN,” describes the MCF548 implementation of the cont

MCF548x Reference Manual, Rev. 317-14 Freescale Semiconductor4. FBCSn is negated at the fourth rising clock edge. This last clock of the bus cycle use

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-1517.6.5 FlexBus Timing Examples17.6.5.1 Basic Read Bus CycleDuring

MCF548x Reference Manual, Rev. 317-16 Freescale SemiconductorFigure 17-9. Basic Read Bus Cycle17.6.5.2 Basic Write Bus CycleDuring a write cycle, the

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-17The write cycle timing diagram is shown in Figure 17-11.Figure 17

MCF548x Reference Manual, Rev. 317-18 Freescale SemiconductorFigure 17-12. Single Word Read Transfer with Muxed 32-A / 16-D or Non-Muxed 16-A / 16-DFi

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-19Figure 17-14 illustrates the basic byte read transfer to an 8-bit

MCF548x Reference Manual, Rev. 317-20 Freescale SemiconductorFigure 17-15. Single Byte Write Transfer with Muxed 32-A / 8-D or Non-Muxed 24-A / 8-DFig

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-21Figure 17-17 illustrates the longword write to a 32-bit device.Fi

MCF548x Reference Manual, Rev. 317-22 Freescale SemiconductorFigure 17-18. Basic Read Bus Cycle (No Wait States)Figure 17-19. Basic Write Bus Cycle (N

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-23Figure 17-20. Read Bus Cycle (One Wait State)Figure 17-21. Write

MCF548x Reference Manual, Rev. 3xliv Freescale SemiconductorGeneral InformationThe following documentation provides useful information about the ColdF

MCF548x Reference Manual, Rev. 317-24 Freescale SemiconductorFigure 17-22. Read Bus Cycle with Two Clock Address Setup (No Wait States)Figure 17-23. W

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-25Figure 17-24. Read Cycle with Two Clock Address Hold (No Wait Sta

MCF548x Reference Manual, Rev. 317-26 Freescale SemiconductorFigure 17-26. Write Cycle with Two Clock Address Setup and Two Clock Hold (One Wait State

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-27NOTELine-sized transfers requested by the core or cache are broke

MCF548x Reference Manual, Rev. 317-28 Freescale SemiconductorFigure 17-28. Longword Write Burst to 8-Bit Port 3-1-1-1 (No Wait States)Figure 17-29 sho

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-29Figure 17-30 shows a longword write through an 8-bit device with

MCF548x Reference Manual, Rev. 317-30 Freescale SemiconductorFigure 17-31 illustrates a write burst transfer with one wait state.Figure 17-32. Longwor

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 17-31Figure 17-34. Longword Write Burst to 8-Bit Port 4-1-1-1 (Address

MCF548x Reference Manual, Rev. 317-32 Freescale SemiconductorFigure 17-36. Example of a Misaligned Word Transfer (32-Bit Port)17.6.8 Bus ErrorsThe MCF

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-1Chapter 18 SDRAM Controller (SDRAMC)18.1 IntroductionThis chapter describes configuration

Acronyms and AbbreviationsMCF548x Reference Manual, Rev. 3Freescale Semiconductor xlvlongword A 32-bit data unitx In some contexts, such as signal en

MCF548x Reference Manual, Rev. 318-2 Freescale Semiconductor18.2.3 Block DiagramFigure 18-1. SDRAM Controller Block Diagram18.3 External Signal Descri

External Signal Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-318.3.4 SDRAM Row Address Strobe (RAS)This output is the SDRAM

MCF548x Reference Manual, Rev. 318-4 Freescale Semiconductor18.3.12 SDRAM Clock Enable (SDCKE)This output is the SDRAM clock enable. SDCKE negates to

Interface Recommendations MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-5All memory devices of a single chip select block must have the

MCF548x Reference Manual, Rev. 318-6 Freescale Semiconductor18.4.2 SDRAM SDR ConnectionsFigure 18-2 shows a block diagram of the connections between t

Interface Recommendations MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-7Figure 18-3. MCF548x Connections to DDR SDRAM18.4.4 SDRAM DDR D

MCF548x Reference Manual, Rev. 318-8 Freescale SemiconductorFigure 18-4. MCF548x Connections to 100-pin DDR SDRAM DIMM18.4.5 DDR SDRAM Layout Consider

SDRAM Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-918.4.5.1 Termination ExampleFigure 18-5 shows the recommended termination

MCF548x Reference Manual, Rev. 318-10 Freescale SemiconductorMany commands require a delay before the next command may be issued; sometimes the delay

SDRAM Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-11issue a PALL command to close the active row. Then the SDRAMC issues ACTV

MCF548x Reference Manual, Rev. 3xlvi Freescale SemiconductorEA Effective addressEDO Extended data output (DRAM)FIFO First-in, first-outGPIO General-pu

MCF548x Reference Manual, Rev. 318-12 Freescale Semiconductor18.5.1.5.1 Mode Register DefinitionFigure 18-6 shows the mode register definition. Note t

SDRAM Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-1318.5.1.6 Auto Refresh Command (REF)The memory controller issues auto refr

MCF548x Reference Manual, Rev. 318-14 Freescale Semiconductor18.5.2.1 SDR InitializationSDR initialization requires the following steps:1. After reset

Functional Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-158. Issue a second PALL command. Initialize the SDRAM control registe

MCF548x Reference Manual, Rev. 318-16 Freescale SemiconductorThe SDRAM controller supports all possible XLB transfer sizes. SDRAMs are “burst only” de

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-1718.7.1 SDRAM Drive Strength Register (SDRAMDS)31 30 29 28

MCF548x Reference Manual, Rev. 318-18 Freescale Semiconductor18.7.2 SDRAM Chip Select Configuration Registers (CSnCFG)Any chip select can be enabled o

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-19CS3CFG = 94000019 = 64M @ 0x9400 0000-0x97FF FFFFCS4CFG =

MCF548x Reference Manual, Rev. 318-20 Freescale Semiconductor18.7.4 SDRAM Control Register (SDCR)The SDCR, shown in Figure 18-11, controls SDRAMC oper

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-2118.7.5 SDRAM Configuration Register 1 (SDCFG1)The 32-bit

Terminology and Notational ConventionsMCF548x Reference Manual, Rev. 3Freescale Semiconductor xlviiTerminology and Notational ConventionsTable iii sho

MCF548x Reference Manual, Rev. 318-22 Freescale SemiconductorThe minimum values of certain fields can be different for SDR and DDR SDRAM, even if the

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-2318.7.6 SDRAM Configuration Register 2 (SDCFG2)The 32-bit

MCF548x Reference Manual, Rev. 318-24 Freescale Semiconductor18.8 SDRAM ExampleThis example interfaces two 16M × 16-bit × 4 bank DDR SDRAM components

SDRAM Example MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-2518.8.1 SDRAM Signal Drive Strength SettingsThe SDRAMDS should be programme

MCF548x Reference Manual, Rev. 318-26 Freescale SemiconductorThis configuration results in a value of SDRAMDS = 0x0000_0019, as described in Table 18-

SDRAM Example MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-2718.8.4 SDRAM Configuration 2 Register SettingsThe SDCFG2 register should b

MCF548x Reference Manual, Rev. 318-28 Freescale SemiconductorThis configuration results in a value of SDCR = 0xE10D_0002, as described in Table 18-19.

SDRAM Example MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-2918.8.6 Set the Extended Mode RegisterThe SDMR should be programmed as show

MCF548x Reference Manual, Rev. 318-30 Freescale Semiconductor18.8.8 Issue a PALL commandThe SDCR should be programmed as shown in Figure 18-21. This w

SDRAM Example MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-3118.8.9 Perform Two Refresh CyclesThe SDCR should be programmed as shown in

MCF548x Reference Manual, Rev. 3xlviii Freescale Semiconductor<ea>y,<ea>x Source and destination effective addresses, respectively<labe

MCF548x Reference Manual, Rev. 318-32 Freescale Semiconductor18.8.10 Clear the Reset DLL Bit in the Mode RegisterThe SDMR should be programmed as show

SDRAM Example MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-3318.8.11 Enable Automatic Refresh and Lock Mode RegisterThe SDCR should be

MCF548x Reference Manual, Rev. 318-34 Freescale Semiconductor18.8.12 Initialization CodeThe following assembly code initializes the DDR SDRAM using th

SDRAM Example MCF548x Reference Manual, Rev. 3Freescale Semiconductor 18-35move.l #0x008D0000, d0//Write LMR and clear reset DLLmove.l d0, SDMREnable

MCF548x Reference Manual, Rev. 318-36 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-1Chapter 19 PCI Bus Controller19.1 IntroductionThis chapter details the operation of the P

MCF548x Reference Manual, Rev. 319-2 Freescale Semiconductor• Compatible with PCI 2.2 specification• PCI initiator and target operation• Fully synchro

External Signal Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-319.2.3 Device Select (PCIDEVSEL)The PCIDEVSEL signal is asser

MCF548x Reference Manual, Rev. 319-4 Freescale Semiconductor19.2.13 Target Ready (PCITRDY)The PCITRDY signal is asserted active low by the currently a

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-5MBAR + 0xB68PCITBATR132 Target Base Address Translation Re

Terminology and Notational ConventionsMCF548x Reference Manual, Rev. 3Freescale Semiconductor xlixAddress Calculated effective address (pointer)Bit Bi

MCF548x Reference Manual, Rev. 319-6 Freescale Semiconductor19.3.1 PCI Type 0 Configuration RegistersThe PCI controller supplies a type 0 PCI configur

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-719.3.1.1 Device ID/Vendor ID Register (PCIIDR)—PCI Dword A

MCF548x Reference Manual, Rev. 319-8 Freescale SemiconductorTable 19-4. PCISCR Field DescriptionsBits Name Description31 PE Parity error detected. Thi

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-919.3.1.3 Revision ID/Class Code Register (PCICCRIR)—PCI Dw

MCF548x Reference Manual, Rev. 319-10 Freescale Semiconductor19.3.1.4 Configuration 1 Register (PCICR1)—PCI Dword 3Table 19-5. PCICCRIR Field Descript

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-1119.3.1.5 Base Address Register 0 (PCIBAR0)—PCI Dword 431

MCF548x Reference Manual, Rev. 319-12 Freescale Semiconductor19.3.1.6 Base Address Register 1 (PCIBAR1)—PCI Dword 519.3.1.7 CardBus CIS Pointer Regist

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-13All 32 bits of the register are programmable by the slave

MCF548x Reference Manual, Rev. 319-14 Freescale Semiconductorregisters are accessed primarily internally as offsets of MBAR, but can also be accessed

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-1519.3.2.2 Target Base Address Translation Register 0 (PCIT

MCF548x Reference Manual, Rev. 3Freescale Semiconductor vContentsParagraphNumberTitlePageNumberChapter 1 Overview1.1 MCF548x Family Overview ...

MCF548x Reference Manual, Rev. 3l Freescale SemiconductorTable 2-1/2-3 Add column to indicate whether the signal has a pull-up resistor.These signals

MCF548x Reference Manual, Rev. 319-16 Freescale Semiconductor19.3.2.3 Target Base Address Translation Register 1 (PCITBATR1)19.3.2.4 Target Control Re

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-1719.3.2.5 Initiator Window 0 Base/Translation Address Regi

MCF548x Reference Manual, Rev. 319-18 Freescale Semiconductor19.3.2.6 Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR)The field descr

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-1919.3.2.7 Initiator Window 2 Base/Translation Address Regi

MCF548x Reference Manual, Rev. 319-20 Freescale Semiconductor19.3.2.9 Initiator Control Register (PCIICR)Table 19-15. PCIIWCR Field DescriptionsBits

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-2119.3.2.10 Initiator Status Register (PCIISR)Table 19-16.

MCF548x Reference Manual, Rev. 319-22 Freescale Semiconductor19.3.2.11 Configuration Address Register (PCICAR)Table 19-17. PCIISR Field DescriptionsBi

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-2319.3.3 Communication Subsystem Interface RegistersThe com

MCF548x Reference Manual, Rev. 319-24 Freescale Semiconductor19.3.3.1.2 Tx Start Address Register (PCITSAR)Table 19-19. PCITPSR Field DescriptionsBits

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-2519.3.3.1.3 Tx Transaction Control Register (PCITTCR) 31 3

Terminology and Notational ConventionsMCF548x Reference Manual, Rev. 3Freescale Semiconductor li2.2.6.1/2-22 Add the following after Table 2-4:Figure

MCF548x Reference Manual, Rev. 319-26 Freescale Semiconductor19.3.3.1.4 Tx Enables Register (PCITER) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-2719.3.3.1.5 Tx Next Address Register (PCITNAR) 21 FEE FIFO

MCF548x Reference Manual, Rev. 319-28 Freescale Semiconductor19.3.3.1.6 Tx Last Word Register (PCITLWR) 19.3.3.1.7 Tx Done Counts Register (PCITDCR) T

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-2919.3.3.1.8 Tx Status Register (PCITSR) Table 19-25. PCITD

MCF548x Reference Manual, Rev. 319-30 Freescale SemiconductorNOTERegisters MBAR + 0x8420 through MBAR + 0x843C are reserved forfuture use. Accesses to

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-3119.3.3.1.9 Tx FIFO Data Register (PCITFDR) +19.3.3.1.10 T

MCF548x Reference Manual, Rev. 319-32 Freescale Semiconductor19.3.3.1.11 Tx FIFO Control Register (PCITFCR) Table 19-28. PCITFSR Field DescriptionsBit

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-3319.3.3.1.12 Tx FIFO Alarm Register (PCITFAR) Table 19-29.

MCF548x Reference Manual, Rev. 319-34 Freescale Semiconductor19.3.3.1.13 Tx FIFO Read Pointer Register (PCITFRPR) Table 19-30. PCITFAR Field Descripti

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-3519.3.3.1.14 Tx FIFO Write Pointer Register (PCITFWPR)This

MCF548x Reference Manual, Rev. 3lii Freescale Semiconductor10.2/10-5 Insert the following section before section 10.2 “XL Bus Arbiter”.10.2 PLL10.2.1

MCF548x Reference Manual, Rev. 319-36 Freescale Semiconductor19.3.3.2.1 Rx Packet Size Register (PCIRPSR) 19.3.3.2.2 Rx Start Address Register (PCIRSA

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-3719.3.3.2.3 Rx Transaction Control Register (PCIRTCR) Tabl

MCF548x Reference Manual, Rev. 319-38 Freescale Semiconductor19.3.3.2.4 Rx Enables Register (PCIRER) 12 FB Full burst. This is the full burst bit and

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-39Table 19-36. PCIRER Field DescriptionsBits Name Descripti

MCF548x Reference Manual, Rev. 319-40 Freescale Semiconductor19.3.3.2.5 Rx Next Address Register (PCIRNAR) 17 IAE Initiator abort enable. User writes

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-4119.3.3.2.6 Rx Done Counts Register (PCIRDCR) 31 30 29 28

MCF548x Reference Manual, Rev. 319-42 Freescale Semiconductor19.3.3.2.7 Rx Status Register (PCIRSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-43NOTERegisters 0x84A0 through 0x84BC are reserved for futu

MCF548x Reference Manual, Rev. 319-44 Freescale Semiconductor19.3.3.2.9 Rx FIFO Status Register (PCIRFSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-4519.3.3.2.10 Rx FIFO Control Register (PCIRFCR) 17 Alarm T

Terminology and Notational ConventionsMCF548x Reference Manual, Rev. 3Freescale Semiconductor liiiTable 10-3/10-5 Bits BA, DT, and AT: The 0 and 1 are

MCF548x Reference Manual, Rev. 319-46 Freescale Semiconductor19.3.3.2.11 Rx FIFO Alarm Register (PCIRFAR) 19 OF_MASK Overflow mask. When this bit is s

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-4719.3.3.2.12 Rx FIFO Read Pointer Register (PCIRFRPR)19.3.

MCF548x Reference Manual, Rev. 319-48 Freescale Semiconductor19.4 Functional DescriptionThe MCF548x PCI module provides both master and target PCI bus

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-4919.4.1.2 Basic Transfer ControlThe basic PCI bus transfer mechani

MCF548x Reference Manual, Rev. 319-50 Freescale Semiconductorcommand driven on the PCICXBE bus. In cycle 2, the AD bus is in a turnaround cycle becaus

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-51Figure 19-48. PCI Write Terminated by Target19.4.1.4 PCI Bus Comm

MCF548x Reference Manual, Rev. 319-52 Freescale SemiconductorThough MCF548x supports many PCI commands as an initiator, the communication subsystem in

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-53As an initiator, the MCF548x supports both linear incrementing an

MCF548x Reference Manual, Rev. 319-54 Freescale Semiconductortells the community of devices on the PCI bus that the bridge that “owns” the PCI bus has

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-55its secondary bus as a Type 0 configuration access, decoding the

MCF548x Reference Manual, Rev. 3liv Freescale Semiconductor21.4.9/21-28 Add the following table below the note at the end of the section and correct t

MCF548x Reference Manual, Rev. 319-56 Freescale SemiconductorFigure 19-52. Initiator Arbitration Block Diagram19.4.2.1 Priority SchemeThe PCI initiato

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-57The particular type of PCI transaction generated is determined by

MCF548x Reference Manual, Rev. 319-58 Freescale Semiconductorrequest to the PCI bus comes in, the data transfer is delayed until all previous writes t

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-59000 100 OP4 OP5 OP6 OP7 — — — — 00 0000 OP7 OP6 OP5 OP4001 100 —

MCF548x Reference Manual, Rev. 319-60 Freescale Semiconductor19.4.4.2 Configuration MechanismIn order to support both Type 0 and Type 1 configuration

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-61The MCF548x can issue PCI configuration transactions to itself. A

MCF548x Reference Manual, Rev. 319-62 Freescale Semiconductor19.4.4.2.2 Type 1 Configuration TranslationFor Type 1 translations, the 30 high-order bit

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-63assigned by the PCI SIG Steering Committee. The current list of d

MCF548x Reference Manual, Rev. 319-64 Freescale SemiconductorUpon detection of a PCI address phase, the PCI controller decodes the address and bus com

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-65Table 19-53. Aligned PCI to XL Bus TransfersPCI Bus XL BusBE[3:0]

Terminology and Notational ConventionsMCF548x Reference Manual, Rev. 3Freescale Semiconductor lv25.1.2/25-2 Add the following section after section 24

MCF548x Reference Manual, Rev. 319-66 Freescale Semiconductor19.4.5.4 Target AbortA target abort will occur if the PCI address falls within a base add

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-67on the XL bus will have 100% bandwidth available to them during P

MCF548x Reference Manual, Rev. 319-68 Freescale Semiconductor19.4.6.3 Data TranslationThe PCI bus is inherently little endian in its byte ordering. Th

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-69If Continuous mode is active, basic operation is still straight f

MCF548x Reference Manual, Rev. 319-70 Freescale Semiconductor19.4.6.9 Bus ErrorsBecause bus errors are particular to the module register set and that

Application Information MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-71read and write requests from an XL bus master and decodes them t

MCF548x Reference Manual, Rev. 319-72 Freescale Semiconductor19.5.2.1 Address Translation19.5.2.1.1 Inbound Address TranslationThe MCF548x-as-target o

Application Information MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-73Figure 19-54. Inbound Address Map19.5.2.1.2 Outbound Address Tra

MCF548x Reference Manual, Rev. 319-74 Freescale SemiconductorFigure 19-55. Outbound Address Map19.5.2.1.3 Base Address Register OverviewTable 19-58 sh

XL Bus Arbitration Priority MCF548x Reference Manual, Rev. 3Freescale Semiconductor 19-7519.6 XL Bus Arbitration PriorityTo prevent XL bus arbitratio

MCF548x Reference Manual, Rev. 3lvi Freescale Semiconductor27.6.1/27-5 Remove instances of MDIS bit as it is not present on this version of the DSPI.T

MCF548x Reference Manual, Rev. 319-76 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 20-1Chapter 20 PCI Bus Arbiter Module20.1 IntroductionThis chapter describes the MCF548x PCI

MCF548x Reference Manual, Rev. 320-2 Freescale Semiconductor20.1.3 Features• Direct support for up to five external PCI bus masters• Fair arbitration

Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 20-320.2.5 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)The PCIBG0

MCF548x Reference Manual, Rev. 320-4 Freescale SemiconductorTable 20-2. PACR Field DescriptionsBits Name Description31 DS Disable bit for the internal

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 20-520.3.2 PCI Arbiter Status Register (PASR)20.4 Functional Descripti

MCF548x Reference Manual, Rev. 320-6 Freescale Semiconductor20.4.2 Arbitration20.4.2.1 Hidden Bus ArbitrationPCI bus arbitration can take place while

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 20-7Figure 20-4. PCI Arbitration Initial State20.4.2.3 Arbitration Lat

MCF548x Reference Manual, Rev. 320-8 Freescale SemiconductorFigure 20-5. Alternating PriorityDevice 0 and device 1 assert REQ while the bus is parked

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 20-9Figure 20-6. Higher Priority OverrideThe arbiter again deasserts d

Terminology and Notational ConventionsMCF548x Reference Manual, Rev. 3Freescale Semiconductor lviiFigure 31-3/Page 31-10 Remove overbar from ALE at lo

MCF548x Reference Manual, Rev. 320-10 Freescale Semiconductorconsidered “broken” and subsequent requests are acknowledged. This “never-mind” scenario

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-1Chapter 21 FlexCAN21.1 IntroductionThe FlexCAN module is a communication controller imple

MCF548x Reference Manual, Rev. 321-2 Freescale SemiconductorFigure 21-2. FlexCAN Message Buffer Architecture21.1.2 The CAN SystemA typical CAN system

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-3bus. It can also provide protection against damage to the FlexCAN caused by

MCF548x Reference Manual, Rev. 321-4 Freescale Semiconductor• The prescaler is disabled, thus halting all CAN bus communication.• The FlexCAN ignores

External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-521.2 External SignalsThe FlexCAN module has two I/O signals connected to

MCF548x Reference Manual, Rev. 321-6 Freescale Semiconductor21.3.2 Register DescriptionsThis section describes the registers in the FlexCAN module. NO

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-7Table 21-2. CANMCR Field DescriptionsBits Name Description

MCF548x Reference Manual, Rev. 321-8 Freescale Semiconductor21.3.2.2 FlexCAN Control Register (CANCTRL)CANCTRL is defined for specific FlexCAN control

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-9Table 21-3. CANCTRL Field DescriptionsBits Name Descriptio

MCF548x Reference Manual, Rev. 3lviii Freescale Semiconductor

MCF548x Reference Manual, Rev. 321-10 Freescale Semiconductor21.3.2.3 FlexCAN Timer Register (TIMER)This register represents a 16-bit free running cou

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-11The timer value is captured at the beginning of the ident

MCF548x Reference Manual, Rev. 321-12 Freescale Semiconductor21.3.2.4.1 FlexCAN Rx Global Mask Register (RXGMASK)The Rx global mask bits are applied t

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-1321.3.2.4.2 FlexCAN Rx 14 Mask Register (RX14MASK)The RX14

MCF548x Reference Manual, Rev. 321-14 Freescale Semiconductor21.3.2.5 FlexCAN Error Counter Register (ERRCNT)This register has two 8-bit fields reflec

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-15to zero and counts in a manner where the internal counter

MCF548x Reference Manual, Rev. 321-16 Freescale SemiconductorTable 21-8 describes the ERRSTAT fields.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R0

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-1721.3.2.7 Interrupt Mask Register (IMASK)IMASK contains on

MCF548x Reference Manual, Rev. 321-18 Freescale SemiconductorTable 21-10 describes the IMASK fields.21.3.2.8 Interrupt Flag Register (IFLAG)IFLAG cont

Functional Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-1921.4 Functional OverviewThe FlexCAN module is flexible in that each

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 1-1Chapter 1 OverviewThis chapter provides an overview of the MCF548x microprocessor feature

MCF548x Reference Manual, Rev. 321-20 Freescale Semiconductor313029282726252423 22 21 20 1918171615141312111098765432100x0 CODE SRR IDE RTR LENGTH TIM

Functional Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-2128–0 ID [28:18] Standard frame identifier: In standard frame format,

MCF548x Reference Manual, Rev. 321-22 Freescale Semiconductor21.4.2 Message Buffer Memory Map The message buffer memory map starts at an offset of 0x8

Functional Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-23Figure 21-13. FlexCAN Message Buffer Memory Map21.4.3 Transmit Proce

MCF548x Reference Manual, Rev. 321-24 Freescale SemiconductorOnce the arbitration process is complete and there is a “winner” MB for transmission, the

Functional Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-25was captured at the beginning of the ID field on the CAN bus) is wri

MCF548x Reference Manual, Rev. 321-26 Freescale Semiconductorlost. Two or more receive MBs that hold a matching ID to a received frame do not assure r

Functional Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-27• There is a point in time until which the deactivation of a Tx MB c

MCF548x Reference Manual, Rev. 321-28 Freescale SemiconductorWhen transmitting a remote frame, the user initializes a message buffer as a transmit mes

Functional Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-29• SYNC_SEG: This segment has a fixed length of one time quantum. Sig

MCF548x Reference Manual, Rev. 3vi Freescale SemiconductorContentsParagraphNumberTitlePageNumber2.2.1.4 Read/Write (R/W) ...

MCF548x Reference Manual, Rev. 31-2 Freescale SemiconductorWith on-chip support for multiple common communications interfaces, MCF548x products requi

MCF548x Reference Manual, Rev. 321-30 Freescale SemiconductorIf PSEG2 equals two, then the FlexCAN transmits one time quantum late relative to the sch

FlexCAN Initialization Sequence MCF548x Reference Manual, Rev. 3Freescale Semiconductor 21-31• If the RXECTR increases to a value greater than 127, i

MCF548x Reference Manual, Rev. 321-32 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-1Chapter 22 Integrated Security Engine (SEC)This chapter provides an overview of the MCF54

MCF548x Reference Manual, Rev. 322-2 Freescale Semiconductordefine the cryptographic function to be performed and the location of the data. The SEC’s

Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-322.4.2 SEC Controller UnitThe SEC controller unit manages on-chip resources, inc

MCF548x Reference Manual, Rev. 322-4 Freescale Semiconductor4. Wait for EU to complete processing.5. Upon completion, unload results and context and w

Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-5Figure 22-2. DES Encryption ProcessIn addition, the DEU module can compute Tripl

MCF548x Reference Manual, Rev. 322-6 Freescale SemiconductorFigure 22-4. RC4 Encryption Process22.4.4.3 Advanced Encryption Standard Execution Unit (A

Overview MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-7• The MDEU also supports HMAC computations, as specified in RFC 2104. With any h

MCF548x Family Products MCF548x Reference Manual, Rev. 3Freescale Semiconductor 1-31.3 MCF548x Family ProductsTable 1-1 summarizes the products avai

MCF548x Reference Manual, Rev. 322-8 Freescale Semiconductor22.4.4.5 Random Number Generator (RNG)The RNG is a digital integrated circuit capable of g

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-90x21008 SIMRH SEC Interrupt Mask Register High p. 22-140x2

MCF548x Reference Manual, Rev. 322-10 Freescale Semiconductor22.6 ControllerThe controller within the SEC core is responsible for overseeing the opera

Controller MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-1122.6.1 EU AccessAssignment of an EU function to a channel is done either stat

MCF548x Reference Manual, Rev. 322-12 Freescale SemiconductorTable 22-4 describes the EUACRH and EUACRL fields.31 30 29 28 27 26 25 24 23 22 21 20 19

Controller MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-1322.6.4.2 EU Assignment Status Registers (EUASRH and EUASRL)The EUASR register

MCF548x Reference Manual, Rev. 322-14 Freescale Semiconductor22.6.4.3 SEC Interrupt Mask Registers (SIMRH and SIMRL)The SEC generates a single interru

Controller MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-15I31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Field CHA_1 CHA_0 AERR —Defin

MCF548x Reference Manual, Rev. 322-16 Freescale Semiconductor22.6.4.6 SEC ID Register (SIDR)The read-only SEC ID register, displayed in Figure 22-13,

Controller MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-1722.6.4.7 SEC Master Control Register (SMCR)The SEC master control register (S

MCF548x Reference Manual, Rev. 31-4 Freescale Semiconductor— Memory management unit (MMU)– Separate, 32-entry, fully-associative instruction and data

MCF548x Reference Manual, Rev. 322-18 Freescale Semiconductor22.6.4.8 Master Error Address Register (MEAR)This register saves the address of the trans

Channels MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-19store the ciphered data the EU outputs. Through a series of requests to the con

MCF548x Reference Manual, Rev. 322-20 Freescale Semiconductor31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R0000000000000000WReset000000000000000015

Channels MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-21Table 22-12 defines the burst size according to the value displayed in the BURS

MCF548x Reference Manual, Rev. 322-22 Freescale Semiconductor31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R0000000000000000WReset0000000000000000151

Channels MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-23Table 22-14. CCPSRLn Field DescriptionsBits Name Description31–27 — Reserved, s

MCF548x Reference Manual, Rev. 322-24 Freescale Semiconductor18 SRD Secondary EU reset done. Reflects the state of the reset done signal from the assi

Channels MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-25Table 22-15 shows the values of crypto-channel states. 8 EUERR EU error. An EU

MCF548x Reference Manual, Rev. 322-26 Freescale Semiconductor0x12 Write mode secondary0x13 Write datasize primary0x14 Delay rng done0x15 Write datasiz

Channels MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-2722.7.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPRn)The CDPR, sh

MCF548x Family Features MCF548x Reference Manual, Rev. 3Freescale Semiconductor 1-5— Execution units for the following:– DES/3DES block cipher– AES

MCF548x Reference Manual, Rev. 322-28 Freescale SemiconductorTable 22-17 describes the FRn fields.22.7.1.5 Data Packet Descriptor Buffer (CDBUFn)This

ARC Four Execution Unit (AFEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-29hardware reset, software reset, or module initialization,

MCF548x Reference Manual, Rev. 322-30 Freescale SemiconductorFigure 22-22. AFEU Status Register (AFSR)Table 22-19 describes AFEU status register field

ARC Four Execution Unit (AFEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-3122.8.4 AFEU Interrupt Status Register (AFISR)The interrup

MCF548x Reference Manual, Rev. 322-32 Freescale Semiconductor22.8.5 AFEU Interrupt Mask Register (AFIMR)The interrupt mask register, shown in Figure 2

ARC Four Execution Unit (AFEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-33Figure 22-24. AFEU Interrupt Mask Register (AFIMR)Table 2

MCF548x Reference Manual, Rev. 322-34 Freescale Semiconductor22.9 Data Encryption Standard Execution Units (DEU)This section contains details about th

Data Encryption Standard Execution Units (DEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-35Figure 22-25. DEU Reset Control Register

MCF548x Reference Manual, Rev. 322-36 Freescale SemiconductorFigure 22-26. DEU Status Register (DSR)Table 22-23 describes the DEU status register’s bi

Data Encryption Standard Execution Units (DEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-3722.9.4 DEU Interrupt Status Register (DIS

MCF548x Reference Manual, Rev. 31-6 Freescale SemiconductorThe ColdFire V4e processor contains a double-precision floating point unit (FPU). The FPU

MCF548x Reference Manual, Rev. 322-38 Freescale Semiconductor29 OFE Output FIFO error. The DEU output FIFO was detected non-empty upon write of DEU da

Data Encryption Standard Execution Units (DEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-3922.9.5 DEU Interrupt Mask Register (DIMR)

MCF548x Reference Manual, Rev. 322-40 Freescale Semiconductor22.10 Message Digest Execution Unit (MDEU)This section contains details about the message

Message Digest Execution Unit (MDEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-4122.10.2 MDEU Reset Control Register (MDRCR)This reg

MCF548x Reference Manual, Rev. 322-42 Freescale SemiconductorFigure 22-30. MDEU Status Register (MDSR)Table 22-27 describes MDEU status register field

Message Digest Execution Unit (MDEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-4322.10.4 MDEU Interrupt Status Register (MDISR)The i

MCF548x Reference Manual, Rev. 322-44 Freescale Semiconductor22.10.5 MDEU Interrupt Mask Register (MDIMR)The MDEU interrupt mask register, shown in Fi

Message Digest Execution Unit (MDEU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-45Figure 22-32. MDEU Interrupt Mask Register (MDIMR)T

MCF548x Reference Manual, Rev. 322-46 Freescale Semiconductor22.11 RNG Execution Unit (RNG)The RNG is an execution unit capable of generating 32-bit r

RNG Execution Unit (RNG) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-4722.11.3 RNG Status Register (RNGSR)This RNG status register, Fi

MCF548x Family Features MCF548x Reference Manual, Rev. 3Freescale Semiconductor 1-7boundary-scan register, and a 32-bit ID register). The boundary s

MCF548x Reference Manual, Rev. 322-48 Freescale Semiconductor22.11.4 RNG Interrupt Status Register (RNGISR)The RNG interrupt status register tracks th

RNG Execution Unit (RNG) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-49Table 22-32 describes RNG interrupt status register fields.22.1

MCF548x Reference Manual, Rev. 322-50 Freescale Semiconductor22.12 Advanced Encryption Standard Execution Units (AESU)This section contains details a

Advanced Encryption Standard Execution Units (AESU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-51Figure 22-36. AESU Reset Control Re

MCF548x Reference Manual, Rev. 322-52 Freescale SemiconductorFigure 22-37. AESU Status Register (AESSR)Table 22-35 describes AESU status register fiel

Advanced Encryption Standard Execution Units (AESU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-5322.12.4 AESU Interrupt Status Regis

MCF548x Reference Manual, Rev. 322-54 Freescale Semiconductor22.12.5 AESU Interrupt Mask Register (AESIMR)The AESU interrupt mask register, shown in F

Advanced Encryption Standard Execution Units (AESU) MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-55and the interrupt status register i

MCF548x Reference Manual, Rev. 322-56 Freescale Semiconductor22.13 DescriptorsAs an IPSec accelerator, the SEC has been targeted for ease of use and i

Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-57Figure 22-40. Data Packet Descriptor Format 22.13.1.1 Descriptor HeaderDescr

MCF548x Reference Manual, Rev. 31-8 Freescale Semiconductor1.4.6 Communications I/O Subsystem1.4.6.1 DMA ControllerThe communications subsystem conta

MCF548x Reference Manual, Rev. 322-58 Freescale Semiconductor Table 22-38. Header Bit DefinitionsBits Name Description31–28 PEUSEL Primary execution u

Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-59Table 22-39 shows the permissible values for the descriptor TYPE field in th

MCF548x Reference Manual, Rev. 322-60 Freescale Semiconductor22.13.1.2 Descriptor Length and Pointer FieldsThe length and pointer fields represent one

Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-6122.13.1.3 Null FieldsOn occasion, a descriptor field may not be applicable t

MCF548x Reference Manual, Rev. 322-62 Freescale SemiconductorFigure 22-45. Chain of Descriptors22.13.3 Descriptor Type FormatsThe SEC accepts 12 fixe

Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-63Table 22-44 shows how the length/pointer pairs should be used with the vario

MCF548x Reference Manual, Rev. 322-64 Freescale Semiconductor22.13.4 Descriptor ClassesThe SEC has two general classes of descriptors: dynamic, which

Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-6522.13.4.2 Static DescriptorsRecall that the SEC has five execution units and

MCF548x Reference Manual, Rev. 322-66 Freescale SemiconductorThe middle (and multiple subsequent) descriptors contains length/pointer pairs to the rem

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-67Because the key and context are unchanging over mult

MCF548x Family Features MCF548x Reference Manual, Rev. 3Freescale Semiconductor 1-9• 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint de

MCF548x Reference Manual, Rev. 322-68 Freescale SemiconductorThe AFEU mode bits do not control cryptographic modes, only operational modes. Therefore,

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-69Table 22-51 shows the descriptor format to load a pr

MCF548x Reference Manual, Rev. 322-70 Freescale SemiconductorTable 22-53 shows the descriptor format to load a previously generated context into the A

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-71Table 22-54 shows the descriptor format for the midd

MCF548x Reference Manual, Rev. 322-72 Freescale Semiconductor22.14.2 DEU Mode Options and Data Packet DescriptorsFigure 22-47 shows the DEU options th

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-7322.14.2.1 Dynamically Assigned DEUFor IPSec processi

MCF548x Reference Manual, Rev. 322-74 Freescale Semiconductor22.14.2.2 Statically Assigned DEUWhen statically assigned, it can be assumed that no othe

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-75Table 22-61 shows the middle descriptor that perform

MCF548x Reference Manual, Rev. 322-76 Freescale SemiconductorTable 22-63 shows the final descriptor that performs a cipher on data using the key and o

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-7722.14.3 MDEU Mode Options and Data Packet Descriptor

MCF548x Reference Manual, Rev. 31-10 Freescale Semiconductor• DMA support1.4.6.7 Controller Area Network (CAN)The FlexCAN modules are communication c

MCF548x Reference Manual, Rev. 322-78 Freescale SemiconductorThe MDEU implements hardware accelerated hashing of data using MD5, SHA-160, or SHA-256.B

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-79(outbound) or compare the hash generated by the SEC

MCF548x Reference Manual, Rev. 322-80 Freescale SemiconductorTable 22-70 lists several different descriptors that use the format shown in Table 22-69.

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-81Table 22-72 lists several different descriptors that

MCF548x Reference Manual, Rev. 322-82 Freescale SemiconductorTable 22-74 lists several different descriptors that use the final MDEU descriptor format

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-8322.14.5 AESU Mode Options and Data Packet Descriptor

MCF548x Reference Manual, Rev. 322-84 Freescale Semiconductor22.14.5.1 Dynamically Assigned AESUTable 22-77 shows a descriptor for a dynamically assig

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-85Table 22-78 lists several different descriptors that

MCF548x Reference Manual, Rev. 322-86 Freescale SemiconductorTable 22-80 lists several different descriptors that use the format shown in Table 22-79.

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-87Table 22-83 shows the final descriptor for a statica

MCF548x Family Features MCF548x Reference Manual, Rev. 3Freescale Semiconductor 1-11frequency from 33–66 MHz. The Flexbus is targeted to support ext

MCF548x Reference Manual, Rev. 322-88 Freescale Semiconductor22.14.5.3 AESU-CCM Mode DescriptorThe SEC supports single pass, single descriptor AES-CCM

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-89Table 22-87 shows the format used for the context ou

MCF548x Reference Manual, Rev. 322-90 Freescale SemiconductorTable 22-89 shows the format used for the context input for AES-CCM.Table 22-87 shows the

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-91such that the same data read into the DEU, AESU, or

MCF548x Reference Manual, Rev. 322-92 Freescale SemiconductorDEU/AESU and MDEU only reading the portion that matches the starting address and byte len

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-93Table 22-93 lists typical AESU/HMAC multi-function d

MCF548x Reference Manual, Rev. 322-94 Freescale Semiconductorcopy the last 8 bytes of the ciphertext to the Security Association Database Entry for th

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-95Table 22-96 lists typical AESU/HMAC multi-function d

MCF548x Reference Manual, Rev. 322-96 Freescale SemiconductorTable 22-98 lists typical DEU/HMAC multi-function descriptor header values for the first

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-97Table 22-99 lists typical AESU/HMAC multi-function d

MCF548x Reference Manual, Rev. 3Freescale Semiconductor viiContentsParagraphNumberTitlePageNumber2.2.5.1 Reset In (RSTI) ...

MCF548x Reference Manual, Rev. 31-12 Freescale Semiconductor1.4.11.2 Interrupt ControllerThe interrupt controller on the MCF548x family can support u

MCF548x Reference Manual, Rev. 322-98 Freescale SemiconductorTable 22-100 shows the representative descriptor format for the middle descriptors in a s

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-99Table 22-102 lists typical AESU/HMAC multi-function

MCF548x Reference Manual, Rev. 322-100 Freescale SemiconductorTable 22-103 shows the representative descriptor format for the final descriptor in a st

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-101Table 22-104 lists typical DEU/HMAC multi-function

MCF548x Reference Manual, Rev. 322-102 Freescale SemiconductorTable 22-105 lists typical AESU/HMAC multi-function descriptor header values.22.14.6.4 S

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-103performs the HMAC function first, then attaches the

MCF548x Reference Manual, Rev. 322-104 Freescale SemiconductorTable 22-107 lists several different descriptor header values that can be used for the o

EU Specific Data Packet Descriptors MCF548x Reference Manual, Rev. 3Freescale Semiconductor 22-105The primary EU is the AFEU, with its mode bits set

MCF548x Reference Manual, Rev. 322-106 Freescale SemiconductorTable 22-111 lists several different descriptor header values that can be used for the o

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 23-1Chapter 23 IEEE 1149.1 Test Access Port (JTAG)23.1 IntroductionThe Joint Test Action Grou

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-1Chapter 2 Signal Descriptions2.1 IntroductionThis chapter describes the MCF548x signals. N

MCF548x Reference Manual, Rev. 323-2 Freescale Semiconductor23.1.2 FeaturesThe basic features of the JTAG module are the following:• Performs boundary

External Signal Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 23-3When one module is selected, the inputs into the other module

MCF548x Reference Manual, Rev. 323-4 Freescale Semiconductor23.2.1.5 Test Reset/Development Serial Clock (TRST/DSCLK)The TRST pin is an active low asy

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 23-523.3.2.3 Bypass RegisterThe bypass register is a single-bi

MCF548x Reference Manual, Rev. 323-6 Freescale Semiconductor23.3.2.6 Boundary Scan RegisterThe boundary scan register is connected between TDI and TDO

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 23-7Figure 23-3. TAP Controller State Machine Flow23.4.3 JTAG Instruct

MCF548x Reference Manual, Rev. 323-8 Freescale Semiconductor23.4.3.1 External Test Instruction (EXTEST)The EXTEST instruction selects the boundary sca

Initialization/Application Information MCF548x Reference Manual, Rev. 3Freescale Semiconductor 23-923.4.3.4 ENABLE_TEST_CTRL InstructionThe ENABLE_TE

MCF548x Reference Manual, Rev. 323-10 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor iPart IVCommunications SubsystemPart IV contains chapters that discuss the operation and confi

MCF548x Reference Manual, Rev. 32-2 Freescale SemiconductorFigure 2-1. MCF548x SignalsMCF548xE0MDIO / PFECI2C3E0CRS / PFEC0H0E0TXD[3:1] / PFEC0L[7:5]E

MCF548x Reference Manual, Rev. 3ii Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-1Chapter 24 Multichannel DMA 24.1 IntroductionThe MCF548x’s direct memory access controlle

MCF548x Reference Manual, Rev. 324-2 Freescale Semiconductor24.1.2 OverviewThe DMA controller processes microcode tasks that are stored in memory. A t

External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-324.2 External Signals24.2.1 DREQ[1:0] These active-low inputs provide ex

MCF548x Reference Manual, Rev. 324-4 Freescale Semiconductor24.3.1.3 Variable TableEach task has a private 48-longword variable table. Typically, each

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-5Figure 24-2. DMA Programmer-Maintained Memory Model24.3.3

MCF548x Reference Manual, Rev. 324-6 Freescale Semiconductor24.3.3.2 Task Base Address Register (TaskBAR)Note that there is a 512-byte alignment restr

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-724.3.3.3 Current Pointer (CP)31 30 29 28 27 26 25 24 23 2

MCF548x Reference Manual, Rev. 324-8 Freescale Semiconductor24.3.3.4 End Pointer (EP)24.3.3.5 Variable Pointer (VP)31 30 29 28 27 26 25 24 23 22 21 20

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-924.3.3.6 PTD Control (PTD)The priority task decode contro

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-3Table 2-1 lists the signals for the MCF548x in functional group order.Table 2

MCF548x Reference Manual, Rev. 324-10 Freescale Semiconductor24.3.3.7 DMA Interrupt Pending (DIPR)24.3.3.8 DMA Interrupt Mask Register (DIMR)31 30 29

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-1124.3.3.9 Task Control Registers (TCRn)Each of the sixtee

MCF548x Reference Manual, Rev. 324-12 Freescale Semiconductor24.3.3.10 Priority Registers (PRIORn)When the PTD Control register bit 15 is set to a log

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-1324.3.3.11 Initiator Mux Control Register (IMCR)The DMA s

MCF548x Reference Manual, Rev. 324-14 Freescale Semiconductor24.3.3.12 Task Size Registers (TSKSZ[0:1])Each of the 16 tasks can be programmed to use s

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-1531 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16TASK0 TAS

MCF548x Reference Manual, Rev. 324-16 Freescale Semiconductor24.3.3.13 Debug Comparator Registers (DBGCOMPn)24.3.3.14 Debug Control (DBGCTL)31 30 29 2

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-17Table 24-14 below shows the encodings for the comparator

MCF548x Reference Manual, Rev. 324-18 Freescale SemiconductorTable 24-15 below shows the encodings for the bits. These bits are set to 101 at reset si

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-1924.3.3.16 PTD Debug RegistersThe PTD Debug register allo

MCF548x Reference Manual, Rev. 32-4 Freescale SemiconductorM2, M3 SDBA[1:0] — — — SDRAM bank addressesO24LowE3 RAS — — — SDRAM row address strobeO24Hi

MCF548x Reference Manual, Rev. 324-20 Freescale Semiconductor24.3.4 External Request Module RegistersThe following section shows the registers contain

Memory Map/Register Definitions MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-2124.3.4.3 External Request Address Mask Register (EREQMAS

MCF548x Reference Manual, Rev. 324-22 Freescale Semiconductor24.4 Functional DescriptionThe DMA controller processes microcode tasks that are stored i

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-23The details of creating task code is beyond the scope of this doc

MCF548x Reference Manual, Rev. 324-24 Freescale Semiconductor24.4.5 PrioritizationThe multichannel DMA has two basic prioritization schemes to decide

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-25function descriptor table. Each data routing descriptor can use t

MCF548x Reference Manual, Rev. 324-26 Freescale Semiconductor24.4.9 Line BuffersThe multichannel DMA makes use of line buffers in its interface to the

Programming Model MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-2724.4.10 Termination of LoopWhile executing an inner loop, there are tw

MCF548x Reference Manual, Rev. 324-28 Freescale Semiconductor4. Priority registers - These will typically only be set during initialization, but can b

Programming Model MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-29The base address for context save space is used to save variables and

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-5D24 PCIIRDY ———PCI initiator ready I/O 16 Hi-ZF23 PCIPAR — — — PCI parity I/O

MCF548x Reference Manual, Rev. 324-30 Freescale Semiconductor24.6 Timing DiagramsThe following timing diagrams show the three modes of external reques

Timing Diagrams MCF548x Reference Manual, Rev. 3Freescale Semiconductor 24-31DACKto assert (clock 5). The next falling edge of DREQ occurs during clo

MCF548x Reference Manual, Rev. 324-32 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 25-1Chapter 25 Comm Timer Module (CTM)25.1 IntroductionThis chapter contains a detailed descr

MCF548x Reference Manual, Rev. 325-2 Freescale SemiconductorFigure 25-2. Fixed Timer Channel Conceptual Block DiagramFigure 25-3. Variable Timer Chann

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 25-3The fixed timer channel provides the user with two modes,

MCF548x Reference Manual, Rev. 325-4 Freescale Semiconductor 25.2.2 Register Descriptions25.2.2.1 Comm Timer Configuration Register (CTCRn)—Fixed Time

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 25-525.2.2.2 Comm Timer Configuration Register (CTCRn)—Variabl

MCF548x Reference Manual, Rev. 325-6 Freescale SemiconductorNOTEThe initiator mode is different from that of a fixed channel in that the periodis vari

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 25-725.3 Functional Description25.3.1 Variable Timer in Baud Clock Gen

MCF548x Reference Manual, Rev. 32-6 Freescale SemiconductorAD8, AC6, AF7 E0TXD[3:1] PFEC0L[7:5] — — MAC transmit data O:I/O 8 GPIAE9 E0TXER PFEC0L4 —

MCF548x Reference Manual, Rev. 325-8 Freescale Semiconductoris deasserted, and the percent counter stops counting and retains a value of 0x3. As befor

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 25-9At the rising edge of the clock in cycle 8, the cAcknowledge signa

MCF548x Reference Manual, Rev. 325-10 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-1Chapter 26 Programmable Serial Controller (PSC)26.1 IntroductionThis chapter describes th

MCF548x Reference Manual, Rev. 326-2 Freescale Semiconductor• Backward compatible with the MC68681— 5,6,7,8 bits data plus parity— Odd, even, none, or

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-326.2.4 PSCnTXDPSCnTXD are the transmitter serial data outp

MCF548x Reference Manual, Rev. 326-4 Freescale Semiconductor0x860C 0x870C 0x880C 0x890C PSC Receive Buffer PSCRBRPSC Transmit BufferPSCTBW0x8610 0x87

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-526.3.3 Register DescriptionsThis section gives detailed de

MCF548x Reference Manual, Rev. 326-6 Freescale Semiconductor26.3.3.2 Mode Register 2 (PSCMR2n)PSCMR2 controls some of the module configuration. It is

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-776543210 ModeR CM TXRTS TXCTS SB UARTWRCM TXRTSTXCTS0000 S

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-7AC24 DSPISIN PDSPI1 PSC3RXD — QSPI data in I:I/O 24 GPIAD22 DSPISCK PDSPI2 PS

MCF548x Reference Manual, Rev. 326-8 Freescale Semiconductor26.3.3.3 Status Register (PSCSRn)The PSCSR register indicates the status of the characters

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-9Table 26-5. PSCSRn Field DescriptionsBits NameDescription1

MCF548x Reference Manual, Rev. 326-10 Freescale Semiconductor26.3.3.4 Clock Select Register (PSCCSRn)The comm timers (CTMs) or the PSC’s timer (see Se

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-11The upper 4 bits set the receiver and the lower 4 bits se

MCF548x Reference Manual, Rev. 326-12 Freescale SemiconductorTable 26-7. PSCCRn Field DescriptionsBits Value Command Description7 — Reserved, should b

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-133–2TXC Field (This field selects a single command)00 NO A

MCF548x Reference Manual, Rev. 326-14 Freescale Semiconductor26.3.3.6 Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn)Data is read from the Rx

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-15Figure 26-10 shows the modem 16 register.Figure 26-11 sho

MCF548x Reference Manual, Rev. 326-16 Freescale SemiconductorTable 26-8 shows the fields for Modem 8, SIR, MIR, and FIR modes.Table 26-9 shows the fie

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-1726.3.3.7 Input Port Change Register (PSCIPCRn)PSCIPCRn sh

MCF548x Reference Manual, Rev. 32-8 Freescale SemiconductorTimer ModuleAD19 TIN3 PTIM7 IRQ3 CANRX1 Timer input I:I/O 8 GPIAD23 TOUT3 PTIM6 CANTX1 — Ti

MCF548x Reference Manual, Rev. 326-18 Freescale Semiconductor26.3.3.8 Auxiliary Control Register (PSCACRn)PSCACR controls the handshake of the transmi

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-1926.3.3.10 Interrupt Mask Register (PSCIMRn)The PSCIMR sel

MCF548x Reference Manual, Rev. 326-20 Freescale Semiconductor15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ModeRIPC 0 0 0 0 0 RXRDY_FU TXRDY DEOF ERR 0 0 0 0

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-2126.3.3.11 Counter Timer Registers (PSCCTURn, PSCCTLRn)The

MCF548x Reference Manual, Rev. 326-22 Freescale Semiconductor26.3.3.13 Output Port Bit Set (PSCOPSETn)Output ports are asserted by writing to this reg

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-2326.3.3.15 PSC/IrDA Control Register (PSCSICRn)This regist

MCF548x Reference Manual, Rev. 326-24 Freescale Semiconductor26.3.3.16 Infrared Control Register 1 (PSCIRCR1n)This register controls the configuration

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-2526.3.3.18 Infrared SIR Divide Register (PSCIRSDRn)26.3.3.

MCF548x Reference Manual, Rev. 326-26 Freescale Semiconductor26.3.3.20 Infrared FIR Divide Register (PSCIRFDRn)This register sets the baud rate in FIR

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-2726.3.3.21 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSC

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-9Power SuppliesC16, C22, E24, H24, M24, R3, U24, Y3, AA24, AB3, AD7, AD10, AD1

MCF548x Reference Manual, Rev. 326-28 Freescale SemiconductorReads from the PSCRFDRn register return received data from the Rx FIFO. In addition, this

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-29Table 26-30. PSCRFSRn and PSCTFSRn Field DescriptionsBits

MCF548x Reference Manual, Rev. 326-30 Freescale Semiconductor26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn)The FIFO control registers

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-3131 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0 0 WFR

MCF548x Reference Manual, Rev. 326-32 Freescale Semiconductor26.3.3.25 Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn)26.3.3.26 Rx and Tx FIFO Read

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-33provided through a port to the FIFO controller. The read

MCF548x Reference Manual, Rev. 326-34 Freescale Semiconductorthere are no safeguards to prevent retransmitting data which has been overwritten. When F

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-3526.4 Functional DescriptionThis section provides a complete funct

MCF548x Reference Manual, Rev. 326-36 Freescale SemiconductorFigure 26-28. Modem Control and TransmitterIf PSCnRTS is programmed to be RxRTS, the PSCn

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-37A/D bit is set or as a data character if the A/D bit is cleared.

MCF548x Reference Manual, Rev. 3viii Freescale SemiconductorContentsParagraphNumberTitlePageNumber2.2.11 I2C I/O Signals ...

MCF548x Reference Manual, Rev. 32-10 Freescale SemiconductorTable 2-2 lists the MCF548x signals in pin number order for the 388 PBGA package.AD164USB_

MCF548x Reference Manual, Rev. 326-38 Freescale SemiconductorFigure 26-30. Waveform of Modem8 ModeThe transmitter starts to transmit the first bit at

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-39Figure 26-31. Waveform of Modem16 ModeThe function of this mode i

MCF548x Reference Manual, Rev. 326-40 Freescale Semiconductor26.4.5.1 TransmitterThe transmitter starts to transmit the first bit at the one clock aft

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-41Leaving low power mode can be done via either a warm or cold rese

MCF548x Reference Manual, Rev. 326-42 Freescale SemiconductorThe STA represents the start of the frame and the STO represents the end of the frame. Bo

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-43.26.4.9 PSC FIFO SystemThe receive FIFO stack consists of the FIF

MCF548x Reference Manual, Rev. 326-44 Freescale Semiconductorare unaffected, and PSCSRn[ERR] sets when the receiver detects the start bit of the new o

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-45NOTEIn AC97, the number of data bytes are four times the number o

MCF548x Reference Manual, Rev. 326-46 Freescale Semiconductor26.4.10 Looping ModesThe UART can be configured to operate in various looping modes as sh

Resets MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-47is ignored, the TxD is held marking, and the receiver is clocked by the transmitt

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-11A21 PSTDDATA1— — — R13 VSS — — —A22 PSTDDATA3— — — R14 VSS — — —A23 PSTDDATA

MCF548x Reference Manual, Rev. 326-48 Freescale Semiconductor26.6 InterruptsThis section describes interrupts originated by this module.26.6.1 Descrip

Software Environment MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-4926.7.2 Configuration26.7.2.1 UART ModeThe following is a sample ini

MCF548x Reference Manual, Rev. 326-50 Freescale Semiconductor26.7.2.2 Modem8 ModeApplying the clock to the PSCBCLK input and programming the control r

Software Environment MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-5126.7.2.3 Modem16 ModeThe configuration sequence in modem16 mode is

MCF548x Reference Manual, Rev. 326-52 Freescale Semiconductor26.7.2.5 SIR ModeHere is a sample configuration sequence in SIR mode. 6 PSCRFAR 00F0 ALAR

Software Environment MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-5326.7.2.6 MIR ModeApplying clock to the PSCBCLK input and programmin

MCF548x Reference Manual, Rev. 326-54 Freescale Semiconductor26.7.2.7 FIR ModeApplying the clock to the PSCBCLK input and programming the control regi

Software Environment MCF548x Reference Manual, Rev. 3Freescale Semiconductor 26-5526.7.3 ProgrammingIn any mode, after the configuration sequence, en

MCF548x Reference Manual, Rev. 326-56 Freescale SemiconductorAfter initialization and after enabling the receiver, the receiver is ready to receive da

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-1Chapter 27 DMA Serial Peripheral Interface (DSPI)This chapter describes the use of the DM

MCF548x Reference Manual, Rev. 32-12 Freescale SemiconductorB261E1RXD2 PFEC1L2 — —V2 AD2 — — —C1 SDVDD— ——V3AD4 — — —C2 CAS — ——V4IVDD — — —C3 VSS — —

MCF548x Reference Manual, Rev. 327-2 Freescale Semiconductor27.3 Block DiagramFigure 27-1 shows a DSPI with external queues in system RAM.Figure 27-1.

Signal Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-327.5 Signal Description27.5.1 OverviewTable 27-1 lists the DSPI signal

MCF548x Reference Manual, Rev. 327-4 Freescale Semiconductor27.5.2.4 DSPI Serial Input (DSPISIN)DSPISIN is a serial data input signal.27.5.2.5 DSPI Se

Memory Map and Registers MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-527.6.1 DSPI Module Configuration Register (DMCR)The DMCR contain

MCF548x Reference Manual, Rev. 327-6 Freescale Semiconductor25 PCSSE Peripheral chip select strobe enable. Selects between the DSPICS5 and PCSS functi

Memory Map and Registers MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-727.6.2 DSPI Transfer Count Register (DTCR)The DTCR contains a co

MCF548x Reference Manual, Rev. 327-8 Freescale Semiconductoran SPI master, the DTFR[CTAS] field in the command portion of the Tx FIFO entry selects wh

Memory Map and Registers MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-921–20 PASC After DSPISCK delay prescaler. The PASC field selects

MCF548x Reference Manual, Rev. 327-10 Freescale Semiconductor7–4 DT Delay after transfer scaler. The DT field selects the delay after transfer scaler.

Memory Map and Registers MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-1127.6.4 DSPI Status Register (DSR)The DSR contains status and fl

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-13D5 SDDATA28— — — AB1 AD12 — — —D6 VSS— — — AB2 AD15 — — —D7 SDADDR2 — — — AB

MCF548x Reference Manual, Rev. 327-12 Freescale SemiconductorTable 27-9. DSR Field DescriptionsBits Name Description31 TCF Transfer complete flag. The

Memory Map and Registers MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-1327.6.5 DSPI DMA/Interrupt Request Select Register (DIRSR)The DI

MCF548x Reference Manual, Rev. 327-14 Freescale SemiconductorDIRSR Field DescriptionsBits Name Description31 TCFE Transfer complete flag interrupt ena

Memory Map and Registers MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-1527.6.6 DSPI Tx FIFO Register (DTFR)The DTFR provides a means to

MCF548x Reference Manual, Rev. 327-16 Freescale Semiconductor27.6.7 DSPI Rx FIFO Register (DRFR)The DRFR provides a means to read the Rx FIFO. See Sec

Memory Map and Registers MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-1727.6.8 DSPI Tx FIFO Debug Registers 0–3 (DTFDRn)The DTFDRn regi

MCF548x Reference Manual, Rev. 327-18 Freescale Semiconductor 27.7 Functional DescriptionThe DMA serial peripheral interface (DSPI) block provides a s

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-19Figure 27-11. SPI Serial Protocol OverviewThe DSPI has four perip

MCF548x Reference Manual, Rev. 327-20 Freescale SemiconductorState transitions from running to stopped occur on the next frame boundary if a transfer

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-21for successful communication with an SPI master. These SPI slave

MCF548x Reference Manual, Rev. 32-14 Freescale SemiconductorF2 SDDQS1— — — AC24 DSPISIN PDSPI1 PSC3RXD —F3 SDVDD— ——AC25DACK1PDMA3 TOUT1 —F4 VSS — — —

MCF548x Reference Manual, Rev. 327-22 Freescale Semiconductor27.7.2.5 Rx FIFO Buffering MechanismThe Rx FIFO functions as a buffer for data received o

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-2327.7.3.1 Baud Rate GeneratorThe baud rate is the frequency of the

MCF548x Reference Manual, Rev. 327-24 Freescale SemiconductorEqn. 27-7Table 27-18 shows an example of how to compute the delay after transfer.27.7.3.5

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-2527.7.4 Transfer FormatsThe SPI serial communication is controlled

MCF548x Reference Manual, Rev. 327-26 Freescale SemiconductorFigure 27-15. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)The master initi

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-27Figure 27-16. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, F

MCF548x Reference Manual, Rev. 327-28 Freescale SemiconductorFigure 27-17. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, Fsck = Fsys/4)27.7.4.4 M

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-29be visible on the master DSPISCK pin during the sampling of the l

MCF548x Reference Manual, Rev. 327-30 Freescale Semiconductor(tDT) is not inserted between the transfers. Figure 27-20 shows the timing diagram for tw

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-31Figure 27-21. Continuous DSPISCK Timing Diagram (CSCK = 0)If DTFR

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-15K1 SDWE— — — AE3 AD28 — — —K2 SDDATA0— — — AE4 AD27 — — —K3 SDDATA1 — — — AE

MCF548x Reference Manual, Rev. 327-32 Freescale SemiconductorEach condition has a flag bit in the Section 27.6.4, “DSPI Status Register (DSR)” and a r

Initialization and Application Information MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-3327.8 Initialization and Application Informati

MCF548x Reference Manual, Rev. 327-34 Freescale Semiconductor27.8.3 Delay SettingsTable 27-23 shows the values for the delay after transfer (tDT) and

Initialization and Application Information MCF548x Reference Manual, Rev. 3Freescale Semiconductor 27-3527.8.4 Calculation of FIFO Pointer AddressesT

MCF548x Reference Manual, Rev. 327-36 Freescale SemiconductorFigure 27-23. Tx FIFO Pointers and Counter27.8.4.1 Address Calculation for the First-in E

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-1Chapter 28 I2C Interface28.1 IntroductionThis chapter describes the I2C™ module, includin

MCF548x Reference Manual, Rev. 328-2 Freescale Semiconductor28.1.2 I2C OverviewI2C is a two-wire, bidirectional serial bus which provides a simple, ef

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-328.3 Memory Map/Register Definition28.3.1 I2C Register Map

MCF548x Reference Manual, Rev. 328-4 Freescale Semiconductor28.3.2.2 I2C Frequency Divider Register (I2FDR)The I2FDR, shown in Figure 28-3, provides a

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-528.3.2.3 I2C Control Register (I2CR)The I2CR is used to en

MCF548x Reference Manual, Rev. 32-16 Freescale Semiconductor2.2 MCF548x External Signals2.2.1 FlexBus Signals2.2.1.1 Address/Data Bus (AD[31:0])The AD

MCF548x Reference Manual, Rev. 328-6 Freescale Semiconductor76543210R ICF IAAS IBB IAL 0 SRW IIF RXAKWReset10000001RegAddrMBAR + 0x8F0CFigure 28-5. I2

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-728.3.2.5 I2C Data I/O Register (I2DR)While in master-recei

MCF548x Reference Manual, Rev. 328-8 Freescale Semiconductor28.4 Functional DescriptionThe I2C has a simple bidirectional 2-wire bus for efficient int

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-9Normally, a standard communication is composed of four parts: STAR

MCF548x Reference Manual, Rev. 328-10 Freescale SemiconductorData can be changed only while SCL is low and must be held stable while SCL is high, as F

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-1128.4.6 Repeated StartA repeated START signal is a START signal ge

MCF548x Reference Manual, Rev. 328-12 Freescale SemiconductorDevices with shorter low periods enter a high wait state during this time (see Figure 28-

Initialization Sequence MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-132. Update the I2ADR to define it as a slave device (give it a sl

MCF548x Reference Manual, Rev. 328-14 Freescale Semiconductor/* Wait for I2SR.IBB (bus busy) to be set */while ( !(MCF5_I2C_I2SR & MCF_I2C_I2SR_BB

Initialization Sequence MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-1528.5.3 Generation of STOPA data transfer ends with a STOP signal

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-172.2.1.2 Chip Select (FBCS[5:0])FBCS[5:0] are asserted to indicat

MCF548x Reference Manual, Rev. 328-16 Freescale Semiconductor/* Generate STOP by clearing I2CR.MSTA */MCF_I2C_I2CR = 0x80;}/*Store received data and r

Initialization Sequence MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-17/* Set I2CR.MTX to put the module in transit mode */MCF_I2C_I2CR

MCF548x Reference Manual, Rev. 328-18 Freescale Semiconductor/* Receive data from master device and store in rx-buffer */for(i=0; i<rx_byte_count;

Initialization Sequence MCF548x Reference Manual, Rev. 3Freescale Semiconductor 28-19Figure 28-14. Flow-Chart of Typical I2C Interrupt RoutineClear I

MCF548x Reference Manual, Rev. 328-20 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-1Chapter 29 USB 2.0 Device Controller29.1 IntroductionThis chapter provides an overview of

MCF548x Reference Manual, Rev. 329-2 Freescale Semiconductor29.1.3 Block DiagramA block diagram of the complete USB 2.0 Device controller module is sh

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-329.1.3.3 FIFO ControllerThe FIFO controller implements the data FIFOs in suc

MCF548x Reference Manual, Rev. 329-4 Freescale Semiconductor29.1.3.5.4 USBCLKINInput pin for the 12-MHz USB crystal circuit.29.1.3.5.5 USBCLKOUTOutput

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-50xB088 USB PID error counter register, USB framing error c

MCF548x Reference Manual, Rev. 32-18 Freescale SemiconductorFor burst-inhibited transfers, TSIZ[1:0] changes with each ALE assertion to reflect the ne

MCF548x Reference Manual, Rev. 329-6 Freescale Semiconductor0xB164 EP2 OUT interface number register, EP2 OUT status registerEP2OUTIFR EP2OUTSR — —0xB

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-70xB1D0– 0xB1D7Reserved0xB1D8 EP4 IN attribute control regi

MCF548x Reference Manual, Rev. 329-8 Freescale Semiconductor0xB23C EP6 IN interface number register, EP6 IN status registerEP6INIFR EP6INSR — —0xB240–

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-929.2.2 USB Request, Control, and Status RegistersThe follo

MCF548x Reference Manual, Rev. 329-10 Freescale Semiconductor29.2.2.2 USB Control Register (USBCR)The USBCR configures features of the module.6–4 — Re

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-11Table 29-3. USBCR Field DescriptionsBits Name Description

MCF548x Reference Manual, Rev. 329-12 Freescale Semiconductor29.2.2.3 USB Descriptor RAM Control Register (DRAMCR)1 APPLOCK Application Lock. This bit

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-1329.2.2.4 USB Descriptor RAM Data Register (DRAMDR)The DRA

MCF548x Reference Manual, Rev. 329-14 Freescale Semiconductor29.2.2.5 USB Interrupt Status Register (USBISR)The USBISR maintains the status of interru

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-1529.2.2.6 USB Interrupt Mask Register (USBIMR)Setting a bi

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-192.2.2.3 SDRAM Bank Addresses (SDBA[1:0])Each SDRAM module has fo

MCF548x Reference Manual, Rev. 329-16 Freescale Semiconductor29.2.2.7 USB Application Interrupt Status Register (USBAISR)The USBAISR contains informat

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-1729.2.2.8 USB Application Interrupt Mask Register (USBAIMR

MCF548x Reference Manual, Rev. 329-18 Freescale Semiconductor29.2.2.9 Endpoint Info Register (EPINFO)The EPINFO contains the currently active endpoint

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-1929.2.2.10 USB Configuration Value Register (CFGR)29.2.2.1

MCF548x Reference Manual, Rev. 329-20 Freescale Semiconductor29.2.2.12 USB Device Speed Register (SPEEDR)The SPEEDR contains the current USB operating

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-2129.2.2.13 USB Frame Number Register (FRMNUMR)29.2.2.14 US

MCF548x Reference Manual, Rev. 329-22 Freescale Semiconductor29.2.2.15 USB Application Interface Update Register (IFUR)The IFUR is used by the USB app

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-2329.2.3 USB Counter RegistersThe USB module contains a num

MCF548x Reference Manual, Rev. 329-24 Freescale Semiconductor29.2.3.2 USB Dropped Packet Counter Register (DPCNT)29.2.3.3 USB CRC Error Counter Regist

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-2529.2.3.5 USB PID Error Counter Register (PIDECNT)29.2.3.6

MCF548x Reference Manual, Rev. 3Freescale Semiconductor ixContentsParagraphNumberTitlePageNumberChapter 3 ColdFire Core3.1 Core Overview ...

MCF548x Reference Manual, Rev. 32-20 Freescale Semiconductor2.2.2.14 SDRAM Reference Voltage (VREF)This is the input reference voltage for differentia

MCF548x Reference Manual, Rev. 329-26 Freescale Semiconductor29.2.3.7 USB Transmitted Packet Counter Register (TXPCNT)29.2.3.8 USB Counter Overflow Re

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-2729.2.4 Endpoint Context RegistersThe endpoint registers a

MCF548x Reference Manual, Rev. 329-28 Freescale Semiconductor29.2.4.2 Endpoint n Max Packet Size Register (EP0MPSR, EPnOUTMPSR, EPnINMPSR)The endpoint

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-2929.2.4.3 Endpoint n Interface Number Register (EP0IFR, EP

MCF548x Reference Manual, Rev. 329-30 Freescale Semiconductor29.2.4.4 Endpoint n Status Register (EP0SR, EPnOUTSR, EPnINSR)The endpoint status registe

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-3129.2.4.5 bmRequest Type Register (BMRTR)The BMRTR records

MCF548x Reference Manual, Rev. 329-32 Freescale Semiconductor29.2.4.6 bRequest Type Register (BRTR)The BRTR records the bRequest field of a SETUP tran

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-3329.2.4.8 wIndex Register (WINDEXR)The WINDEXR records the

MCF548x Reference Manual, Rev. 329-34 Freescale SemiconductorWhen the host directs a SYNCH_FRAME control read query at this register’s endpoint, the c

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-3529.2.5.2 USB Endpoint n Interrupt Status Register (EPnISR

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-212.2.3.9 Reset (PCIRESET)The PCIRESET signal is asserted active l

MCF548x Reference Manual, Rev. 329-36 Freescale SemiconductorIf a register write occurs at the same time an interrupt is received, the interrupt takes

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-3729.2.5.3 USB Endpoint n Interrupt Mask Register (EPnIMR)T

MCF548x Reference Manual, Rev. 329-38 Freescale Semiconductor29.2.5.4 USB Endpoint n FIFO RAM Configuration Register (EPnFRCFGR)The EPnFRCFGR allows t

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-3929.2.5.5 USB Endpoint n FIFO Data Register (EPnFDR)The EP

MCF548x Reference Manual, Rev. 329-40 Freescale Semiconductor29.2.5.6 USB Endpoint n FIFO Status Register (EPnFSR)Table 29-40. EPnFDR Field Descriptio

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-4123 FAE Frame accept error. This bit indicates a frame acc

MCF548x Reference Manual, Rev. 329-42 Freescale Semiconductor29.2.5.7 USB Endpoint n FIFO Control Register (EPnFCR)31 30 29 28 27 26 25 24 23 22 21 20

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-4326-24 GR Granularity. The functionality of this field dep

MCF548x Reference Manual, Rev. 329-44 Freescale Semiconductor29.2.5.8 USB Endpoint n FIFO Alarm Register (EPnFAR)31 30 29 28 27 26 25 24 23 22 21 20 1

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-4529.2.5.9 USB Endpoint n FIFO Read Pointer (EPnFRP)29.2.5.

MCF548x Reference Manual, Rev. 32-22 Freescale Semiconductor2.2.5 Clock and Reset SignalsThe clock and reset signals configure the MCF548x and provide

MCF548x Reference Manual, Rev. 329-46 Freescale Semiconductor29.2.5.11 USB Endpoint n Last Read Frame Pointer (EPnLRFP)Table 29-45. EPnFWP Field Descr

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-4729.2.5.12 USB Endpoint n Last Write Frame Pointer (EPnLWFP)29.3 F

MCF548x Reference Manual, Rev. 329-48 Freescale SemiconductorAt power-up time, the USB module contains no configuration information. The USB module do

Software Interface MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-49Download of the descriptor data consists of the following steps:1. Ve

MCF548x Reference Manual, Rev. 329-50 Freescale Semiconductor29.4.1.4 FIFO SizesFIFO sizes must be programmed to match the traffic sent across the US

Software Interface MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-5129.4.3.1 USB PacketsData moves across the USB in units called packets

MCF548x Reference Manual, Rev. 329-52 Freescale Semiconductor2. On receiving EOF interrupt, prepare to read a complete packet of data. Clear the EOF i

Software Interface MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-53further requests from the host. This guarantees that data from two di

MCF548x Reference Manual, Rev. 329-54 Freescale Semiconductor4. Handle the request appropriately. If a data transfer is implied by the command, set up

Software Interface MCF548x Reference Manual, Rev. 3Freescale Semiconductor 29-5529.4.3.8 Isochronous OperationsIsochronous operations are a special c

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-23Figure 2-2. CLKIN, Internal Bus, and Core Clock Ratios2.2.6.2 AD

MCF548x Reference Manual, Rev. 329-56 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-1Chapter 30 Fast Ethernet Controller (FEC)30.1 Introduction This Fast Ethernet Controller

MCF548x Reference Manual, Rev. 330-2 Freescale SemiconductorFigure 30-1. FEC Block Diagram30.1.3 OverviewThe Fast Ethernet Controller is designed to s

Introduction MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-330.1.4 FeaturesThe FEC incorporates the following features:• Support for thr

MCF548x Reference Manual, Rev. 330-4 Freescale Semiconductortransceiver via this interface in the following sections: Section 30.4.3, “Network Interfa

External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-530.2.5 Transmit Error (EnTXER)Assertion of this output signal for one or

MCF548x Reference Manual, Rev. 330-6 Freescale Semiconductor.A false carrier condition occurs if the PHY detects a bad start-of-stream delimiter. This

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-730.3.2 Detailed Memory Map (Control/Status Registers)Table

MCF548x Reference Manual, Rev. 330-8 Freescale Semiconductor30.3.3 MIB Block Counters Memory MapTable 30-6 defines the MIB Counters memory map which d

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-9which are supported do not require MIB counters. Counters

MCF548x Reference Manual, Rev. 32-24 Freescale Semiconductor2.2.6.5 AD2—Auto Acknowledge Configuration (AACONFIG)At reset, the enabling and disabling

MCF548x Reference Manual, Rev. 330-10 Freescale Semiconductor30.3.3.1 Ethernet Interrupt Event Register (EIR)When an event occurs that sets a bit in t

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-11Interrupts resulting from errors/problems detected in the

MCF548x Reference Manual, Rev. 330-12 Freescale Semiconductor30.3.3.2 Interrupt Mask Register (EIMR)The EIMR controls which possible interrupt events

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-1330.3.3.3 Ethernet Control Register (ECR)ECR is a read/wri

MCF548x Reference Manual, Rev. 330-14 Freescale Semiconductor30.3.3.4 MII Management Frame Register (MMFR)The MMFR is accessed by the user and does no

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-15To perform a read or write operation on the MII Managemen

MCF548x Reference Manual, Rev. 330-16 Freescale SemiconductorThe MII_SPEED field must be programmed with a value to provide an EMDC frequency of less

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-1730.3.3.6 MIB Control Register (MIBC)The MIBC is a read/wr

MCF548x Reference Manual, Rev. 330-18 Freescale Semiconductor30.3.3.8 Receive Hash Register (RHR)This read only register provides address recognition

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-1930.3.3.9 Transmit Control Register (TCR)The TCR is read/w

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-252.2.7.2 Management Data Clock (E0MDC, E1MDC)EMDC is an output cl

MCF548x Reference Manual, Rev. 330-20 Freescale Semiconductor30.3.3.10 Physical Address Low Register (PALR)The PALR is written by the user. This regis

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-2130.3.3.11 Physical Address High Register (PAHR)The PAHR i

MCF548x Reference Manual, Rev. 330-22 Freescale Semiconductor30.3.3.12 Opcode/Pause Duration Register (OPD)The OPD is read/write accessible. This regi

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-2330.3.3.14 Individual Address Lower Register (IALR)The IAL

MCF548x Reference Manual, Rev. 330-24 Freescale Semiconductor30.3.3.15 Group Address Upper Register (GAUR)The GAUR is written by the user. This regist

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-2530.3.3.17 FEC Transmit FIFO Watermark Register (FECTFWR)T

MCF548x Reference Manual, Rev. 330-26 Freescale Semiconductor30.3.3.18 FEC Receive FIFO Data Register (FECRFDR)This is the main interface port for the

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-2731 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R IP 0 0 0

MCF548x Reference Manual, Rev. 330-28 Freescale Semiconductor30.3.3.20 FEC Receive FIFO Control Register (FECRFCR)The FIFO receive control register pr

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-2931 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R000TIMERF

MCF548x Reference Manual, Rev. 32-26 Freescale Semiconductor2.2.7.12 Transmit Error (E0TXER, E1TXER)When the ETXER output is asserted for one or more

MCF548x Reference Manual, Rev. 330-30 Freescale Semiconductor30.3.3.21 FEC Receive FIFO Last Read Frame Pointer Register (FECRLRFP)The last read frame

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-31in-between the read and write pointers) into framed and u

MCF548x Reference Manual, Rev. 330-32 Freescale Semiconductor30.3.3.24 FEC Receive FIFO Read Pointer Register (FECRFRP)The read pointer is a FIFO main

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-3330.3.3.25 FEC Receive FIFO Write Pointer Register (FECRFW

MCF548x Reference Manual, Rev. 330-34 Freescale Semiconductor30.3.3.27 FEC Transmit FIFO Status Register (FECTFSR)The FIFO transmit status register co

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-35Table 30-34. FECTFSR Field DescriptionsBits Name Descript

MCF548x Reference Manual, Rev. 330-36 Freescale Semiconductor30.3.3.28 FEC Transmit FIFO Control Register (FECTFCR)The FIFO transmit control register

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-3730.3.3.29 FEC Transmit FIFO Last Read Frame Pointer Regis

MCF548x Reference Manual, Rev. 330-38 Freescale Semiconductor30.3.3.30 FEC Transmit FIFO Last Write Frame Pointer Register (FECTLWFP)The last read fra

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-3930.3.3.31 FEC Transmit FIFO Alarm Register (FECTFAR)This

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-272.2.9.2 DSPI Synchronous Serial Data Input (DSPISIN)The DSPISIN

MCF548x Reference Manual, Rev. 330-40 Freescale Semiconductor30.3.3.32 FEC Transmit FIFO Read Pointer Register (FECTFRP)The read pointer is a FIFO mai

Memory Map/Register Definition MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-4130.3.3.34 FEC FIFO Reset Register (FECFRST)The FIFO’s wit

MCF548x Reference Manual, Rev. 330-42 Freescale Semiconductor30.3.3.35 FEC CRC and Transmit Frame Control Word Register (FECCTCWR)The FEC can be sent

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-4330.4 Functional DescriptionThis section describes the operation o

MCF548x Reference Manual, Rev. 330-44 Freescale Semiconductor30.4.2 Frame Control/Status WordsIn the FEC, transmit frame control words and receive fra

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-4530.4.2.2 Transmit Frame Control Word (TFCW)Figure 30-40 shows the

MCF548x Reference Manual, Rev. 330-46 Freescale Semiconductor30.4.3 Network Interface OptionsThe FEC supports both an MII interface for 10/100 Mbps Et

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-47When the transmit FIFO fills to the watermark (defined by FECTFWR

MCF548x Reference Manual, Rev. 330-48 Freescale SemiconductorDuring reception, the Ethernet controller checks for various error conditions and once th

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-49Figure 30-41. Ethernet Address Recognition—Receive Block Decision

MCF548x Reference Manual, Rev. 32-28 Freescale Semiconductor2.2.11.1 Serial Clock (SCL)This bidirectional open-drain signal is the clock signal for th

MCF548x Reference Manual, Rev. 330-50 Freescale SemiconductorThe hash table registers must be initialized by the user. The CRC32 polynomial to use in

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-5159:FF:FF:FF:FF:FF 0x1C 2879:FF:FF:FF:FF:FF 0x1D 2929:FF:FF:FF:FF:

MCF548x Reference Manual, Rev. 330-52 Freescale Semiconductor30.4.8 Full Duplex Flow ControlFull-duplex flow control allows the user to transmit pause

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-53The user must specify the desired pause duration in the OPD regis

MCF548x Reference Manual, Rev. 330-54 Freescale Semiconductortransmit side and/or limit the size of the frames to prevent transmit FIFO underrun and r

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-5530.4.12.2 Reception Errors30.4.12.2.1 Overrun Error If the recei

MCF548x Reference Manual, Rev. 330-56 Freescale SemiconductorThe data portion of the frame consists of N octets which corresponds to 2N nibbles being

Functional Description MCF548x Reference Manual, Rev. 3Freescale Semiconductor 30-574 Auto-Negotiation (AN) AdvertisementE5 AN Link Partner Ability E

MCF548x Reference Manual, Rev. 330-58 Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor iPart VMechanicalPart V provides mechanical descriptions of the MCF548x.Contents• Chapter 31,

MCF548x External Signals MCF548x Reference Manual, Rev. 3Freescale Semiconductor 2-292.2.14 Timer Module SignalsThe signals in the following sections

MCF548x Reference Manual, Rev. 3ii Freescale Semiconductor

MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-1Chapter 31 Mechanical DataThis chapter contains drawings showing the pinout, packaging, a

MCF548x Reference Manual, Rev. 331-2 Freescale SemiconductorA22 PSTDDATA3— — — R14 VSS — — —A23 PSTDDATA7 — — — R15 VSS — — —A24 PCIBR0 PPCIBR0 TIN0 —

Pinout MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-3C1 SDVDD — — — V3 AD4 — — —C2 CAS — ——V4IVDD — — —C3 VSS — — — V23 DSPICS3 PDSPI5

MCF548x Reference Manual, Rev. 331-4 Freescale SemiconductorD6 VSS— — — AB2 AD15 — — —D7 SDADDR2 — — — AB3 EVDD — — —D8 SDADDR6 — — — AB4 VSS — — —D9

Pinout MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-5F3 SDVDD — ——AC25DACK1 PDMA3 TOUT1 —F4 VSS — — — AC26 PSC2TXD PPSC3PSC20 — —F23 PC

MCF548x Reference Manual, Rev. 331-6 Freescale SemiconductorK2 SDDATA0— — — AE4 AD27 — — —K3 SDDATA1 — — — AE5 R/W PFBCTL2 TBST —K4 SDDATA11 — — — AE6

Pinout MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-7M23 VSS — — — AF9 E0TXCLK PFEC0H7 — —M24 EVDD — — — AF10 E0MDIO PFECI2C3 — —M25 PC

MCF548x Reference Manual, Rev. 331-8 Freescale Semiconductor31.3 Mechanical Diagrams31.3.1 MCF5485/5484 Mechanical DiagramFigure 31-1–Figure 31-4 show

Mechanical Diagrams MCF548x Reference Manual, Rev. 3Freescale Semiconductor 31-9Figure 31-2 shows the pinout for the upper right quadrant of the MCF5