Freescale-semiconductor MPC5200B Manuale Utente Scaricare il pdf (Pagina 120)

100

101

Overview

MPC5200B Users Guide, Rev. 1

Freescale Semiconductor 3-1

Chapter 3

Memory Map

3.1 Overview

The following sections are contained in this document:

• MPC5200B Internal Register Memory Map

• MPC5200B Memory Map

• SDRAM Bus

• LocalPlus Bus

— Memory Cycles

– Boot Chip Select

– Chip Selects

— ATA Cycles

— PCI Cycles

• MPC5200B Register Summaries

— Memory Map Registers -- MBAR + 0x0000

— SDRAM Registers -- MBAR + 0x0100

— Clock Distribution Module Registers -- MBAR + 0x0200

— Chip Select Configuration Registers -- MBAR + 0x0300

— Interrupt Controller Registers -- MBAR + 0x0500

— General Purpose Timer Registers -- MBAR + 0x0600

— Slice Timer Control Registers -- MBAR + 0x0700

— Real Time Clock Registers -- MBAR + 0x0800

— MSCAN Registers -- MBAR + 0x0900

— Simple GPIO Registers -- MBAR + 0x0B00

— Wake-up GPIO Registers -- MBAR + 0x0C00

— PCI Registers -- MBAR + 0x0D00

— Serial Peripheral Interface Registers -- MBAR + 0x0F00

— USB Host Registers -- MBAR + 0x1000

— BestComm Registers -- MBAR + 0x1200

— J1850 (BDLC Controller) Registers -- MBAR + 0x1300

— XL BUS ARbitration Registers -- MBAR + 0x1F00

— PSC1 Registers -- MBAR + 0x2000

— PSC2 Registers -- MBAR + 0x2200

— PSC3 Registers -- MBAR + 0x2400

— PSC4 Registers -- MBAR + 0x2600

— PSC5 Registers -- MBAR + 0x2800

— PSC6 Registers -- MBAR + 0x2C00

— Ethernet Registers -- MBAR + 0x3000

— BestComm / PCI Interface Registers -- MBAR + 0x3800

— ATA Bus Configuration Registers -- MBAR + 0x3A00

— BestComm / LocalPlus Interface Registers -- MBAR + 0x3C00

— I2C Configuration Registers -- MBAR + 0x3D00

— SRAM Module -- MBAR + 0x8000

1 2 ... 115 116 117 118 119 120 121 122 123 124 125 ... 761 762

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